-- file:dpll.vhd
------------------------------------------ 
-- locks to the input frequency  
-- Input is frequency.
-- The Designis from:
-- R.E. Best "phase locked loop 
-- design, simulation and application".
-- 
-- By Ahmed Allam
-- November 1999
-- University of Alberta, EE552.

---------------------------------
-- compiles with no known errors.
---------------------------------
-- Caution: This loop was tested with a 
-- clock = 25.175 MHZ. The center frequency is 
-- 786 Khz. 
-- The lock BW is from 689 Khz to 909 KHz. 
-- From 763khz to 806 khz the lock is weak.
-- The lock can be inproved by utilizing a
-- ripple cancellation circuit as described
-- in the above mentioned reference. The lock can 
-- also be improved by encreasing the modulus of the 
-- K counter. However, the bandwidth will be 
-- reduced.
----------------------------------- 

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 


entity dpll is 
   port (f_in, clock:in std_logic ;
         Fal_test :buffer std_logic; 
         --- signal added for test
         carr_test, borr_test,id_out_test,dlipout,up_down_test,t : out std_logic;
         f_out,data :buffer std_logic
         ); 
end dpll; 

architecture archadll of dpll is 

   component counter4 is
      port(clock, count_up_down : in std_logic;
	   carr, borrow : out std_logic
	  );
   end component;

   component inc_dec is
      port (carr, borr, clock :in std_logic; 
            --- signal added for test
            dlipout : out std_logic;
            IDout,Flag_test : buffer std_logic
           ); 
   end component;

   component div8 is  
      port(inpu  : in std_logic;
	   fout: buffer std_logic
      );
   end component; 
	
   component d is
      port (inpu_c,d_in:in std_logic ;
            q_out  :buffer std_logic 
           ); 
   end component;

   component ph_det is  
      port (a,b  :in std_logic ;
                qa,qb: out std_logic
              ); 
   end component ; 

   component jk is
      port(input  : in std_logic;
	    q: buffer std_logic
          );
   end component; 

  signal up_down,bo,ca,id_int,clock_int : std_logic;
 
begin 

   u1:counter4
   port map (clock => clock_int,
	     count_up_down => up_down, 
	     carr => ca,
             borrow => bo
            );
    
   u2:inc_dec 
   port map(carr => ca, 
            borr => bo, 
            clock => clock_int, 
            dlipout =>   dlipout,
            IDout => id_int, 
            Flag_test => Fal_test
           );

   u3:div8
   port map(inpu => id_int,
	    fout => f_out 
           );

   u4:d
   port map (inpu_c =>f_out,
     	     d_in => f_in,
             q_out => data
            ); 

  u5:ph_det
  port map (a => f_out ,
            b => f_in,
            qa =>up_down,
            qb => t  -- unused output
           );

   u6:jk 
   port map(input =>clock,
	    q => clock_int -- divides the input clock 
           );               -- by 2.
  
   carr_test   <= ca; 
   borr_test   <= bo;
   id_out_test <= id_int;
   up_down_test <= up_down; 

end archadll;