-- file: dff_cont.vhd
------------------------------------------ 
-- Generates the signal that drives the xor gate 
--  
-- --
-- October 9, 1999
-- University of Alberta, EE552.

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 


entity dff_cont is
   port (
      Flag_carr,Flag_borr,clock: in std_logic; 
      ToggleFF : buffer std_logic; 
      IDout : out  std_logic;
      Flag  : buffer std_logic                           
   ); 
end dff_cont; 


architecture archcon of dff_cont is 

   begin 

   -- Proces that sets the value of the inputs to the 
   -- j and k input of the flip flop.
   dff_control:process (Flag_carr, flag_borr)

   begin 
       if  (Flag_carr= '1' or Flag_borr = '1') then  
	   Flag  <= '0' ;
       else 
           Flag  <= '1';        
       end if ;
   end process  dff_control;


   -- process that changes the frequency of the IDout 

   jk:process (clock)

   begin 
      if clock 'event and clock = '1' then 
         ToggleFF <= (  Flag  and not ToggleFF ) or (not Flag and ToggleFF) ;
       end if ; 
   end process jk;


   IDout <= not clock and not ToggleFF; 

end archcon;