-- file: d.vhd
------------------------------------------ 
--  D-Flip flop
--  
-- input is assigned to the output  
-- at the clock edge
--
-- By Ahmed Allam
-- October 8, 1999
-- University of Alberta, EE552.

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 


entity d is 
	port (inpu_c, d_in:in std_logic ;
          q_out  :buffer std_logic 
         ); 
end d;       
	 
-- output is assigned to the input 
-- at the clcok edge

architecture archd of d is 
begin 
	dflop:process (inpu_c )
	begin 
		if  inpu_c 'event and inpu_c = '1' then 
    			q_out <= d_in;
		end if; 

	end process dflop;
 
end archd;