-------------------------------------------------------------------------------
-- Stream Cipher/Decipher
-- Author       : Tam Paredes
-- File Name    : stream_cipher.vhd
-- Architecture : mixed
-- Description  : This stream cipher XORs a keystream with either plaintext or
--				  ciphertext to produce ciphertext or plaintext, respectively.
--				  The reset and enable signals are active-high.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.stream_cipher_pkg.all;

entity stream_cipher is
	port(clock,reset,enable,data_in :	in std_logic;
		 data_out,valid_stream		:	out std_logic
		);
end stream_cipher;

architecture mixed of stream_cipher is

signal latched_key,
	   latched_data,
	   internal_keystream: std_logic;

begin

	-- Encryption/decryption is done by xor-ing the data bits
	-- with the bits produced by the keystream generator
	data_out <= latched_data xor latched_key;
	valid_stream <= enable;

	key: key_generator
		 port map(clock => clock,
				  reset => reset,
				  enable => enable,
				  output => internal_keystream
				 );

	reg: reg2_1
		 port map(inputA => data_in,
				  inputB => internal_keystream,
				  clock => clock,
				  reset => reset,
				  outputA => latched_data,
				  outputB => latched_key
				 );

end mixed;