-------------------------------------------------------------------------------
-- An 13-bit Maximal Length Linear Feedback Shift Register (LFSR)
-- Author       : Tam Paredes
-- File Name    : shift_reg13.vhd
-- Architecture : Behavioural
-- Description  : This shift register is initialized with a key.  Every clock
--				  cycle, all of the bits in the register are shifted such
--				  that the least significant bit is output.  The new most
--				  significant bit is computed from the XOR of certain bits in
--				  the register.  This shift register is rising edge triggered 
--				  with an active-high enable and active-high reset.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.stream_cipher_pkg.all;

entity shift_reg13 is
	port(clock,reset,enable :	in std_logic;
		 output 			:	out std_logic
		);
end shift_reg13;

architecture behavioural of shift_reg13 is

signal new_bit: std_logic;
signal internal_reg: std_logic_vector(degreeA-1 downto 0);
signal internal_reg_next: std_logic_vector(degreeA-1 downto 0);

begin

	-- XOR bits 13, 4, 3 and 1
	-- Note that indexing starts from 0
	new_bit <= internal_reg(12) xor internal_reg(3) xor internal_reg(2) xor internal_reg(0);

	-- Output is the rightmost bit (LSB) which is shifted out
	output <= internal_reg(0);

	-- To get new register value, shift bits to the right and
	-- place newly calculated bit in most significant position
	internal_reg_next <= new_bit & internal_reg(degreeA-1 downto 1);

	process(clock,reset)
	begin

		if (reset = '1') then
			-- Reset internal_state to the original hard-coded key
			-- Any key is acceptable except all zeros
			internal_reg <= "0000000001101";

		elsif rising_edge(clock) then
			if(enable = '1') then

				-- Determine new value in register
				internal_reg <= internal_reg_next;

			end if;
		end if;
	
	end process;
end behavioural;