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-- Serial to Parallel Data Converter
-- Author       : Tam Paredes
-- File Name    : s_to_p_data_conv.vhd
-- Architecture : behavioural
-- Description  : This data converter takes inputs serially, buffers them until
--				  8 bits have been received, then outputs all 8 bits in parallel.
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity s_to_p_data_conv is
	generic(bit_width: positive := 8);
	port(clock,reset : in std_logic;
		 valid_in	 : in std_logic;   -- Active high
		 serial_in	 : in std_logic;
		 valid_out	 : out std_logic;  -- Active high
		 parallel_out: out std_logic_vector(bit_width-1 downto 0)
		);
end s_to_p_data_conv;

architecture behavioural of s_to_p_data_conv is

-- Declare a new type for the states
type state_type is (wait_v,read0,read1,read2,read3,read4,read5,read6,read7,send);
signal state: state_type;  -- Current state of FSM
signal internal_reg: std_logic_vector(bit_width-1 downto 0);  -- Buffer for serial inputs

begin

	process(clock,reset)
	begin

		if reset = '1' then  -- Active high reset
			state <= wait_v;  -- Return to initial state
		elsif rising_edge(clock) then  -- FSM responds to clock rising edge
			case state is

				when wait_v =>  -- Waiting for valid line to be asserted
					if valid_in = '1' then  -- Input data is valid
						state <= read0;  -- Start reading bits
					elsif valid_in = '0' then  -- Input data is not valid
						state <= wait_v;  -- Wait in this state until data read is valid
					end if;

				when read0 =>  -- Reading in LSB
						internal_reg(0) <= serial_in;  -- Store input
						state <= read1;  -- Read next bit

				when read1 =>  -- Reading bit in position 1
					internal_reg(1) <= serial_in;  -- Store input
					state <= read2;  -- Read next bit

				when read2 =>  -- Reading bit in position 2
					internal_reg(2) <= serial_in;  -- Store input
					state <= read3;  -- Read next bit

				when read3 =>  -- Reading bit in position 3
					internal_reg(3) <= serial_in;  -- Store input
					state <= read4;  -- Read next bit

				when read4 =>  -- Reading bit in position 4
					internal_reg(4) <= serial_in;  -- Store input
					state <= read5;  -- Read next bit

				when read5 =>  -- Reading bit in position 5
					internal_reg(5) <= serial_in;  -- Store input
					state <= read6;  -- Read next bit

				when read6 =>  -- Reading bit in position 6
					internal_reg(6) <= serial_in;  -- Store input
					state <= read7;  -- Read next bit

				when read7 =>  -- Reading in MSB
					internal_reg(7) <= serial_in;  -- Store input
					state <= send;  -- Send all 8 bits at next clock cycle

				when send =>  -- Sending 8 bits in parallel
					if valid_in = '1' then  -- Input data is valid
						state <= read0;  -- Start reading bits
					elsif valid_in = '0' then  -- Input data is not valid
						state <= send;  -- Wait in this state until data read is valid
					end if;

			end case;
		end if;

	end process;

	with state select
		parallel_out <= internal_reg when send,  -- Send 8 bits in parallel
						"00000000" when others;  -- Do not send any valid data

	with state select
		valid_out <= '1' when send,	   -- Indicate output data is valid
					 '0' when others;  -- Indicate output data is not valid

end behavioural;