24-Bit Analog-to-Digital Converter for Audio

by Charlena Fong, Marc Objois, Mariya Shterngartz, and Catherine Single

The A/D stereo audio converter that will be discussed is the CS5360 (A/D) made by Crystal Semiconductors. 

The A/D converter has two inputs, one for the left channel and the other for the right channel.  The incoming data is being sampled at 48 KHz. The converter has a master clock running at 12.288MHz, or 256 times the sampling frequency, 48 KHz. The converter also has a serial clock, running at 64 times the sampling frequency and a clock running at 48 KHz to determine from which channel the data is coming from - '1' for left and '0' for right.  The incoming data from the two channels will output the converter as serial data.

A clock divider is needed to generate the converter's master clock since Altera's FLEX10K20RC240-4 chip has its clock at 25MHz and the converter's master clock runs at 12.288MHz. The serial clock is generated by dividing the converter's master clock's frequency by 4. The left-right clock is generated by dividing the converter's master clock by 256 to get the 48KHz sampling frequency.

The number of incoming serial bits per sampled channel is 32, however, only the first 24 bits contain useful information.  The last 8 bits are the PSL (Peak Signal Level) and indicate the peak level in decibels (see section 4.1 High Resolution Mode in the data sheets).  The signal 'frame' goes high if the PSL bits are detected.   The last 8 bits and signal 'frame' will be ignored here.

The VHDL code is as follows:

-- adc.vhd
-- by Charlena Fong, Marc Objois, Mariya Shterngartz, and Catherine Single
-- EE 552

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity adc is
generic( n : positive := 32;    --audio_input_data_width includes the 8 PSL bits       
            data_width : positive :=24     --audio output data width
             );       

port(audio_in_left : in std_logic; --serial input for the left audio signal
       audio_in_right : in std_logic;    --serial input for the right audio signal
       sdata : out std_logic;    --serial output that outputs audio_in_left and
                                           -- audio_in_right
      sclk : in std_logic; -- serial data clock (from A/D) 64X audio clock
      lrclk : in std_logic -- Left / Right clock
    );
end adc;


architecture behavioral of adc is

begin

process(sclk, lrclk)

variable count1, count2 : integer := 0;

begin

if rising_edge(sclk) then
        if lrclk ='1' then                 --left channel
            count2:=0;    
            count1:=count1+1;
            if count1<=24 then             --count1 is less or equal to 24 when the frame is '0'                                
                sdata <= audio_in_left;
            end if;
               
        elsif lrclk='0' then             --right channel
            count1:=0;    
            count2:=count2+1;                    
            if count2<=24 then          --count2 is less or equal to 24 when the frame is '0'
                sdata <= audio_in_right;   
            end if;            
        end if;
    end if;
   
end process;
end behavioral;