The project includes a 24-bit Crystal Semiconductor Stereo A/D converter (CS 5360). The CS5360 is a 2-channel, single +5 V supply, 24-bit Analog to Digital converter for digital audio systems. The output word rate can be up to 50 kHz per channel.

This component had to be programmed and tested to correctly output the data.

The exciter signal is to be connected to the right channel and the carrier signal is connected to the left channel. The ADC takes 2 analog audio inputs and outputs their digital 24-bit representation interlaced with two sets of 8-bit Peak Signal Level (PSL) bits (I²S format). The serial data then passes through an audio signal decoder, which will convert the serial data stream to 2 parallel 8-bit data stream. The reader is referred to the application note on the A/D converter Interface, which describes the signal decoder in detail.

This project uses the Mater Mode. In this mode, the internal dividers will divide the MCLK by 4 to generate a serial data clock (sclk), which is 64x Fs (the sampling frequency), and by 256 to generate a left/right clock (lrclk), which runs at the Fs.

The CS5360 supports three serial formats. The formats determine the relationship between the format and SDATA, slck and lrclk and are shown on page 10 of the specification sheets. For this project Format 0 was chosen. The corresponding D1F1 and D1F0 pins are grounded.

The A/D converter takes a Mater Clock (MCLK). To produce a MCLK, an Altera clock has to be divided. In our design, initial desired sampling frequency was 44.1kHz. This frequency corresponds to a MCLK of 11.289 and an Altera clock (25.175MHz) that would run at a frequency of Altera/(2.23). To simplify the clock divider function, an Altera clock was divided by 2, the integer closest to 2.23. This corresponds to a MCLK of 12.59 MHz, lrclk of 49.17 kHz and sclk of 3.15 MHz. The sampling frequency is lower than the maximum output word rate of 50kHz per channel.

In this design only the 8 Most Significant Bits per channel of the 24 available bits were used to reduce on the size of the synthesized VHDL code. Also the Peak Signal Level (PSL) were ignored, along with the frame bits that frame the PSL bits.

Sclk is an output in Mater Mode. The internals dividers will divide the MCLK by 4 to generate a serial clock, which is 64x Fs.

The lrclk determines which channel, left or right, is to be output on SDATA. In Master Mode, lrclk is an output whose frequency is equal to Fs ( in this project 49.1 kHz).

When wiring up the A/D Converter, one has to make sure that the analog and digital wires are separated and are not crossed over. Crossing of the wires might create an antenna like effect, which will create noise. Therefore , the support circuitry connected to pins 3, 6, 13, 14, 16, 17 should be kept away from pins 7, 8, 9 and 12, which are the the digital connections. Also, in Mater Mode, pins 2 and 10 have to be connected to 47 kW resistors. Pins 4, 5, 1, 11, 19 and 20 are connected to ground. The reset, pin 18, is connected to the pin that corresponds to the reset pin in the Altera board.