The serial to parallel decoder takes 64-bit serial input and converts it to two 8-bit parallel streams. The input of the serial to parallel decoder is the output of a 24-bit Crystal Semiconductors Stereo Analog to Digital converter (CS5360 model) in the I²S serial format. The I²S serial format contains, in sequence, a 24-bit value representing the current left channel sample, an 8-bit value representing a peak signal level (PSL) detection value for the left channel, a 24-bit value representing the current right channel sample and an 8-bit value representing a PSL detection value for the right channel. To learn more about the A/D converter used to support the A/D converter Interface the reader is referred to the application note on the ADC (CS5360).

The decoder uses two clocks, Serial Clock (Sclk) and Left/Right Clock (lrclk), to output the data. Sclk and lrclk are coming from the ADC. Internal dividers will divide the ADC clock (MCLK) by 4 to generate a Sclk, and by 256 to generate lrclk.

To convert serial 64-bit data to two 8-bit parallel streams, the incoming data is shifted through a 64-bit shift register. After 64 Sclk pulses the resulting 64-bit vector of the shift register contains, in sequence, the left and right digital audio output sequences.

Note that, the stored data in the shift register is the incoming stream stored backwards. Therefore, bits 63 down to 40 in the shift register contain a 24-bit value representing the current left channel sample, bits 39 down to 32 in the shift register contain an 8-bit value representing a peak signal level (PSL) detection value for the left channel, bits 31 down to 8 in the shift register contain a 24-bit value representing the current right channel sample and bits 7 down to 0 in the shift register contain an 8-bit value representing a PSL detection value for the right channel. The process interface_sclk describes the behavior of the shift register.

In this project only the first 8 bits of the left and right channels were used in the internal processing, therefore only the first 8 bits of the left and right incoming data streams will be stored. The purpose of the output shift registers is to store the first 8 bits of the left and right incoming data streams and then output them simultaneously on the next rising edge of the lrclk. To achieve this, two output shift registers, outputA and outputB, store bits 63 to 53 and 31 to 23, respectively and then output those streams when lrclk='1'. The process interface_lrclk describes the behavior of the output shift registers.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.sdt_logic_unsigned.all;

entity decoder is

--sr_size is the size of the shift register

generic( data_output_width : integer :=8; sr_size : integer :=64);

port (sdata : in std_logic;

sclk : in std_logic;

lrclk : in std_logic;

outputA : in std_logic_vector (data_output_width-1 downto 0);

outputB : in std_logic_vector (data_output_width-1 downto 0);

);

end decoder;

architecture behavioral of decoder is

signal sr : std_logic_vector (sr_size-1 downto 0);

begin

interface_sclk : process(sclk)

begin

if rising_edge (sclk) then

sr<=sr(sr_size-2 downto 0) & sdata;

end if;

end process interface_sclk;

interface_lrclk : process(lrclk)

begin

if rising_edge (lrclk) then

outputA<=sr((sr_size-1) downto (sr_size-data_output_width-1));

outputB<=sr((sr_size/2-1) downto (sr_size/2

end if;

end process interface_lrclk;

end behavioral;