Working WITH Altera's Maxplus2...

Submitted by

Andrew Dunmore

 

Anthony Eshpeter

 

One of the most frustrating things about starting to use a new software tool is learning how the tool behaves and what it considers "correct" syntax, especially beyond what is given in the help.

 

This document will list some of the quirks of Altera's Maxplus2 and some of the workarounds that have been discovered to avoid those frustrating stumbling blocks.

 

  1. Problems using lpm_shiftreg with the Maxplus2 STUDENT EDITION.

    2. When looking under the help page for lpm_shiftreg, it mentions that the shift register only needs

    to use one the following input methods: data, aset, aclr, sset, sclr.

     

    Unfortunately, this does not seem to be the case. When trying to use any one input method other than data, an error is given on the generic map line of your code. To work around this problem, you must include a signal attached to the data port of the lpm_shiftreg. This can just be initialized to zero and will not affect the operation of your shift register.

     

  2. Problems assigning values to generic maps in pre-compiled entities.

    3.  

    If you create an entity with a generic mapping, for example:

     

    Entity hum is

    generic ( WIDTH :positive := 8 )

    port ( ... );

    end entity hum;

     

    and then pre-compile it and try to use it as a component in another file, you may find problems trying to reassign the generic variable. For example:

     

    hum1: component hum

    generic map ( WIDTH => 11 )

    port map ( ... );

     

    Altera seems to compile the original file and giving all the internal references to its generic variables their actual values. This does not enable one to define new values for variables outside of the code. The only known work-around right now seems to be to declare new entities for every different variable mappings you need, map the variables appropriately, and then compile them separately. For example, if you need two components of hum, one with WIDTH = 8 and WIDTH = 11, create two entities for hum, both the same, except for their generic mappings and names.

     

     

  3. Creating multiple finite state machines in one architecture

 

Some designs may require many simple finite machines in one architecture. The first solution most people come up with is to declare one set of state types:

TYPE state_type is ( S0, S1, S2, S3 );

 

And then to create multiple state variables for their finite state machine using the one state_type.

 

Signal fsm1, fsm2 : state_type;

 

Maxplus2 does not seem to like it when you use their template for finite state machines and then try to instantiate multiple signals based on the one state type. In order to overcome this, you must (unfortunately) declare two different state types for each finite state machine.

 

TYPE st1 is (S0_1, S1_1, S2_1, S3_1 );

TYPE st2 is (S0_2, S1_2, S2_2, S3_2 );

 

Signal fsm1 : st1;

Signal fsm2 : st2;

 

This will solve the problem.