--
-- timer.vhd
--
-- A generic timer, which takes as input a
-- clock-period-multipler value.  When the
-- internal counter reaches the specified
-- count value, the output line is raised.
--
-- Darren Gould
-- Kevin Grant
-- Andrew Stanley-Jones
--
-- EE 552 Project
-- D. Elliott
--


library ieee;
	use ieee.std_logic_1164.all;
	use ieee.std_logic_arith.all; 
	use ieee.std_logic_unsigned.all; 
library work;


--
-- PACKAGE timer_package
--

package timer_package
is
	component timer
	is
	generic
	(
		clock_period_multiplier:	positive := 25600;	-- this times a 512 kHz clock is 50 ms
		internal_counter_bit_width:	positive := 24		-- number of bits wide the counter will be
	);
	port
	(
		clock:		in std_logic;
		reset:		in std_logic;
		start:		in std_logic;
		
		running:	out std_logic
	);
	end component;
end package;


--
-- ENTITY timer
--

library ieee;
	use ieee.std_logic_1164.all;
	use ieee.std_logic_arith.all; 
	use ieee.std_logic_unsigned.all; 
library work;


entity timer
is
        generic
        (
                clock_period_multiplier:        positive := 25600;  -- this times a 512 kHz clock is 50 ms
                internal_counter_bit_width:     positive := 24      -- number of bits wide the counter will be
        );
        port
        (
                clock:          in std_logic;
                reset:          in std_logic;
                start:          in std_logic;

                running:       out std_logic
        );
end entity timer;


architecture timer_behavior
of timer
is
type	timer_state
	is
	(
		timer_state_idle,
		timer_state_timer_start,
		timer_state_timing
	);
signal	state, next_state: timer_state;
signal	enable: std_logic;
signal	count: std_logic_vector((internal_counter_bit_width - 1) downto 0);
begin
	transition: process(clock)
	begin
		if reset = '1' then
			enable <= '0';
			running <= '0';
			next_state <= timer_state_idle;
		elsif rising_edge(clock) then
			case state is
				when timer_state_idle =>
					enable <= '0';
					if start = '1' then
						running <= '1';
						next_state <= timer_state_timer_start;
					else
						next_state <= timer_state_idle;
						running <= '0';
					end if;
				when timer_state_timer_start =>
					enable <= '1';
					running <= '1';
					if count > clock_period_multiplier then
						next_state <= timer_state_timing;
					else
						next_state <= timer_state_timer_start;
					end if;
				when timer_state_timing =>
					enable <= '0';
					running <= '0';
					if start = '1' then
						next_state <= timer_state_timing;
					else
						next_state <= timer_state_idle;
					end if;
				when others => -- impossible?
					enable <= '0';
					running <= '0';
					next_state <= timer_state_idle;
			end case;
			
			if enable = '1' then
				count <= count + '1';
			else
				count <= (others => '0');
			end if;
		end if;
	end process;
	
	state <= next_state;
end architecture timer_behavior;