VHDL code for a generic timer is available here.

This module makes it easy to express a time delay in terms of the input clock frequency, and to then have a signal assert while the delay takes place. Its direct application is in response to an input from something like a push button, but the design has other applications as well.

The module has two generic maps. The first generic value is clock_period_multiplier, which indicates the length of the delay that the timer provides (the exact time of which depends on the duration of the input clock pulses). The other generic value is internal_counter_bit_width, which allows you to make the counter as big or as small as you need it (it will only store a value between zero and clock_period_multiplier). The default multiplier will produce a delay of fifty milliseconds when the input clock frequency is 512 kHz. The default counter size is 24 bits.

The system has three inputs and one output. The obvious input is the clock signal, whose duration directly affects the delay of the timer. Multiply the clock duration by the clock multiplier to get the time in SI units of seconds. The reset input will zero the counter and set the running output to zero, which causes the delay to cease until start is asserted. The running output rises as soon as start receives a pulse, and remains high until the delay is over.