library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------
-- This code demonstrates the use of lpm_ff and lpm_mult
-- to create a multiplier/adder for DSP purposes.
--
-- It is assumed that the data inputs are of equal width.
-- The sum input and result output are set to a width twice that
--	of the inputs.
-- 
-- The flip flop is used to interface the inputs to the multiplier,
--  allowing Registered Performance Analysis to be performed.
----------------------------------------------------------
-- February 16, 1999
library lpm;
use lpm.lpm_components.all;

entity LPM_mult_tst is
	generic (INPUT_WIDTH: positive := 16;
			 OUTPUT_WIDTH: positive := 32);	-- set to 2*INPUT_WIDTH
	port (dataa: IN STD_LOGIC_VECTOR(INPUT_WIDTH-1 DOWNTO 0);
		datab: IN STD_LOGIC_VECTOR(INPUT_WIDTH-1 DOWNTO 0);
		aclr: IN STD_LOGIC;
		clock: IN STD_LOGIC;
      	sum: IN STD_LOGIC_VECTOR(OUTPUT_WIDTH-1 DOWNTO 0);
      	result: OUT STD_LOGIC_VECTOR(OUTPUT_WIDTH-1 DOWNTO 0));
end LPM_mult_tst;

architecture multiply of LPM_mult_tst is
signal dataa_q,datab_q: STD_LOGIC_VECTOR(INPUT_WIDTH-1 DOWNTO 0);
signal result_d: STD_LOGIC_VECTOR(OUTPUT_WIDTH-1 DOWNTO 0);
signal const_in: STD_LOGIC_VECTOR(INPUT_WIDTH-1 DOWNTO 0);
signal sum_q: STD_LOGIC_VECTOR(OUTPUT_WIDTH-1 DOWNTO 0);
begin

const_in <= "1100000000000000";

Inputaff: lpm_ff
   GENERIC MAP(LPM_WIDTH => INPUT_WIDTH)
   PORT MAP(data => dataa,
      clock => clock,
      aclr => aclr,
      q => dataa_q);

Inputbff: lpm_ff
   GENERIC MAP(LPM_WIDTH => INPUT_WIDTH)
   PORT MAP(data => datab,
      clock => clock,
      aclr => aclr,
      q => datab_q);

Inputsumff: lpm_ff
   GENERIC MAP(LPM_WIDTH => OUTPUT_WIDTH)
   PORT MAP(data => sum,
      clock => clock,
      aclr => aclr,
      q => sum_q);

Mult1: lpm_mult
   GENERIC MAP(LPM_WIDTHA => INPUT_WIDTH,	-- req'd, width of multiplicand
      LPM_WIDTHB => INPUT_WIDTH,			-- req'd, width of multiplier
      LPM_WIDTHS => OUTPUT_WIDTH,			-- req'd, width of sum input
      LPM_WIDTHP => OUTPUT_WIDTH,			-- req'd, width of final result output
      LPM_PIPELINE => 1			-- default 0 pipelines
		)
   PORT MAP(dataa => dataa_q,
		--datab => datab_q,
      	datab => const_in,
		aclr => aclr,
		sum => sum_q,
      clock => clock,
      result => result_d);

Resultff: lpm_ff
   GENERIC MAP(LPM_WIDTH => OUTPUT_WIDTH)
   PORT MAP(data => result_d,
      clock => clock,
      aclr => aclr,
      q => result);

end multiply;