library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------
-- This code demonstrates the use of lpm_ff and lpm_add_sub
-- to create an adder for DSP purposes.
--
-- It is assumed that the data inputs are of equal width.
-- The sum input and result output are set to a width twice that
--	of the inputs.
-- 
-- The flip flop is used to interface the inputs to the multiplier,
--  allowing Registered Performance Analysis to be performed.
----------------------------------------------------------
-- February 22, 1999
library lpm;
use lpm.lpm_components.all;

entity LPM_add_tst is
	generic (INPUT_WIDTH: positive := 16);
	port (dataa: IN STD_LOGIC_VECTOR(INPUT_WIDTH-1 DOWNTO 0);
		datab: IN STD_LOGIC_VECTOR(INPUT_WIDTH-1 DOWNTO 0);
		aclr: IN STD_LOGIC;
		clock: IN STD_LOGIC;
		cout: OUT STD_LOGIC;
      	result: OUT STD_LOGIC_VECTOR(INPUT_WIDTH-1 DOWNTO 0));
end LPM_add_tst;

architecture add of LPM_add_tst is
signal dataa_q: STD_LOGIC_VECTOR(INPUT_WIDTH-1 DOWNTO 0);
signal datab_q: STD_LOGIC_VECTOR(INPUT_WIDTH-1 DOWNTO 0);
signal result_d: STD_LOGIC_VECTOR(INPUT_WIDTH-1 DOWNTO 0);
--signal gnd: std_logic;
begin

--gnd <= '0';

Inputaff: lpm_ff
   GENERIC MAP(LPM_WIDTH => INPUT_WIDTH)
   PORT MAP(data => dataa,
      clock => clock,
      aclr => aclr,
      q => dataa_q);

Inputbff: lpm_ff
   GENERIC MAP(LPM_WIDTH => INPUT_WIDTH)
   PORT MAP(data => datab,
      clock => clock,
      aclr => aclr,
      q => datab_q);

add1: lpm_add_sub
   generic map(LPM_WIDTH => INPUT_WIDTH,
      LPM_REPRESENTATION => "UNSIGNED",
      LPM_DIRECTION => "ADD",
      LPM_PIPELINE => 0)
   port map (dataa => dataa_q, 
		datab => datab_q,
      	aclr => aclr,
--      	clock => clock,
      	result => result_d,
	    cout => cout);

Resultff: lpm_ff
   GENERIC MAP(LPM_WIDTH => INPUT_WIDTH)
   PORT MAP(data => result_d,
      clock => clock,
      aclr => aclr,
      q => result);

end add;