-- LCD output
-- Takes the character codes and outputs them

library ieee; 
library work;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
use work.LCD_types.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 


entity LCDout is
	port (
		clock : in std_logic;
		reset : in std_logic;
		address: in std_logic_vector(addressbit-1 downto 0);
		enable: out std_logic;		
		command : out std_logic_vector(comm_bit -1 downto 0)
	);
end entity LCDout;


architecture behavior of LCDout is

type state_type is (initial, clear, home, writestln1, modeset, displayon, funcset, lastcharln1, writestln2, lastcharln2, changeline);

signal state, nextstate : state_type;
signal char : integer range 0 to num_char-1;
signal count : integer range 0 to cleartime;
signal countval:integer range 0 to cleartime;
signal oldcount:integer range 0 to cleartime;
signal datasig:std_logic_vector(databit-1 downto 0);

signal memdata:std_logic_vector(databit-1 downto 0);

signal charaddress: std_logic_vector(addressbit-1 downto 0);


begin


StartROM : lpm_rom

	GENERIC MAP (LPM_WIDTH => databit,
	LPM_WIDTHAD => (addressbit),
	LPM_TYPE => "L_ROM",
	LPM_FILE => "lcdout.mif") -- note remember to call this initialization file the same as the original file

PORT MAP (address => charaddress,
	inclock => clock,
	outclock => clock,
	q => memdata);





enable_pulse : process (clock)
begin

if rising_edge(clock) then 

	if count = 1 then
		if (state = home) then
						charaddress <= address;
						char<=0;
		else
			if (not(state = changeline)) then
					char <= char +1;		
					charaddress <= charaddress +1;
			end if;
		end if;		
	end if;

	if ((count = oldcount-10)) and (not(state = initial)) then
		enable <= '1';
	else
		enable <= '0';
	end if;

end if;

end process enable_pulse;

display_char : process (clock)
begin
	case state is
	
		when 	initial =>
					nextstate <= funcset;
					countval <= functime;

		when  	funcset =>
					nextstate <= displayon;
					countval <= cleartime;

		when 	displayon =>
					nextstate <= modeset;
					countval <= functime;

		when 	modeset =>
					nextstate <= clear;
					countval <= functime;
		
		when 	clear =>
					nextstate <= home;
					countval <= cleartime;
				
		when 	home =>
					nextstate <= writestln1;
					countval <= writetime;
				
		when 	writestln1 =>				
					datasig<= memdata;

					if char = ((num_char/2)-1) then
						nextstate <= lastcharln1;
						countval<=writetime;
					else
						nextstate <= writestln1;
						countval <= writetime;
					end if;
					

		when 	lastcharln1 =>
					datasig<=memdata;
					nextstate <= changeline;
					countval <= functime;

		when 	changeline =>

					datasig <=memdata;
					nextstate <=writestln2;
					countval <=writetime;
		

		when 	writestln2 =>

					datasig <=memdata;
					if char = ((num_char)-1) then
						nextstate <= lastcharln2;
						countval<=writetime;
					else
						nextstate <= writestln2;
						countval <= writetime;
					end if;

		when 	lastcharln2 =>

					datasig <=memdata;
					nextstate <= home;
					countval <= cleartime;

end case;
end process display_char;


state_register:process(reset,clock)
variable enablecheck : std_logic;
begin
	if ((clock'event) and (clock='1')) then

		-- Synchronouus reset
		if reset = '0' then
			state <= initial ;
			count <= 0;
		-- Change state

		else 
			
			if count = 0 then
				state <= nextstate;
				count <=countval;
				oldcount <=countval;

			else
				count <= count-1;
			end if;

			--end if;

		end if;
	end if;
end process state_register;




with state select

	command <=	"0000000110" when modeset,
				"0000001100" when displayon,
				--"0000001000" when displayoff,
				'1'&'0'&datasig  when writestln1,
				'1'&'0'&datasig  when lastcharln1,
				'1'&'0'&datasig  when writestln2,
				'1'&'0'&datasig  when lastcharln2,
				"0011000000" when changeline,
				"0000000001" when clear,
				"0000000010" when home,
				"0000111000" when funcset,
				"0000000000" when others;

				






end behavior;