VHDL code for an axis-crossing detector is available here (with code for the utility package it uses here).

The crossing detector features a flexible axis that can be specified numerically, while the input sample is a standard logic vector. The sample bit width is also flexible, allowing axis crossings from analog signals to be detected using A/D of virtually any granularity.

The module has two outputs of interest: the sample "sign", a buffered value that indicates which side of the axis the machine believes it is on at the moment, and a "detected zero crossing" output that is raised briefly when a crossing is picked up.

There are also several inputs to the design. In addition to the sample vector (which is used to compare against), there is a "listen" input that is essentially an enabler, a clock input and a synchronous reset input. If the "listen" line is not raised, the system does not try to detect zero-crossings. The reset state of the system is a sign of '1' (positive), with all other lines lowered.

The most common use of these outputs is to operate a counter, which would increment each time a crossing is detected.