Group Members:  Norman Bo, Kelvin Leung, David Ritter

These application notes will discuss the use of Phase Shift Keying as a method of modulating a digital signal, and will provide information on how to implement a PSK transmitter and receiver in an FPGA.

PSK is a form of phase modulation, in which the carrier is modulated by a signal that is digital. As such, changes in the modulating signal will be between two distinct levels, represented by logic 0 and logic 1. As a result, the phase of the modulated signal will instantaneously change between two distinct phases. One method of this is to reverse the sign of sinusoidal carrier. This corresponds to a 180 degree phase change.

The use of a sinusoidal carrier may not be convenient, however, in digital circuitry. A square wave can be used as a carrier as well. The Fourier transform of a square wave contains terms with multiples of the square wave frequency.

Modulating a square wave carrier using PSK can be implemented fairly easily. Two carriers can be generated from a common clock, separated in phase by 90 degrees. To generate these carriers, force a transition on one of the carriers on each rising edge of the common clock.

The following VHDL code will generate two square waves separated by 90 degrees.

entity carrier_gen is
port(osc: in std_logic;
    carrier0: out std_logic;
    carrier1: out std_logic);
end carrier_gen;

architecture behaviour carrier_gen is
begin

osc_logic: process(i_osc)
variable carrier_flag: integer range 1 downto 0 := 0;
begin
    if rising_edge(osc) then
        if carrier_flag = 1 then
            if carrier1 = '1' then
                carrier1 <= '0';
            else
                carrier1 <= '1';
            end if;
            carrier_flag := 0;
        else
            if carrier0 = '1' then
                carrier0 <= '0';
            else
                carrier0 <= '1';
            end if;
            carrier_flag := 1;
        end if;
    end if;
end process osc_logic;

end behaviour;
 

Using this method, the common clock frequency must be 4 times the desired carrier frequency. This common clock can be generated from an external oscillator. If the oscillator frequency is greater that required, the frequency can be divided using a counter.

The two carriers, which correspond to logic 0 and logic 1, can be used as the 0 and 1 inputs to a multiplexer, with the modulating binary signal as the select input:

It is desirable to synchronize the modulating binary signal to one of the carrier waves, to prevent glitches that could otherwise result. Furthermore, requiring data bit transitions to be synchronized with the carrier will simplify receiver design. This will be discussed later in this document.

The following VHDL code implements this design:

entity mux is
port(carrier0: in std_logic;
    carrier1: in std_logic;
    bitstream: in std_logic;
    tx_signal: out std_logic);
end mux;

architecture behaviour of mux is
begin

tx_logic: process(carrier0,carrier1,bitstream)
begin
    if rising_edge(carrier1) then
        if bitstream = '0' then
            tx_signal <= carrier0;
        else
            tx_signal <= carrier1;
        end if;
    end if;
end process tx_logic;

end behaviour;
 

The modulated signal will display a basic square wave shape, with shortened or elongated pulses where transitions occur in the modulating binary signal. With the carrier waves we have shown above, and assuming data bits are synchronized with the rising edge of the logic 1 carrier, elongated pulses of logic 0 indicate data 1 to data 0 transitions.

Shortened pulses of logic 0 indicate 0 to 1 transitions.

As mentioned above, the square wave carrier will contain frequency components at multiples of the carrier frequency. When this signal is received, it must be filtered and amplified. The resulting signal will not contain higher harmonics. The filtered signal will contain only the carrier frequency, and will thus appear as a sinusoid. This signal can be converted to a square wave using a threshold detector. If the threshold level is selected correctly, the square wave will be recovered. Selecting higher or lower threshold values will result in longer or shorter logic level 1 pulses, in effect changing the duty cycle of the square wave. In discussing demodulation of the signal, we will assume that the modulated signal has been recovered in the same form as it was sent.

The design of a demodulator will depend on several factors. This discussion will assume that data transfer is asynchronous, that idle states between transmissions will result in no carrier being transmitted, and that individual transmissions will be signaled using one or more start bits. Also, this discussion will assume that the carrier frequency and the bit transmission frequency are known by the receiver. An exact duplicate of the carrier is not required, however. This will be discussed later.

We have specified that an idle state will result in no carrier being transmitted. Thus, when transmission starts, the start bit will result in a rising edge transition at the receiver. This rising edge will serve to activate the demodulator. Once activated, the demodulator will begin sampling the signal at regular intervals. Sampling should occur at a rate at least 4 times the carrier frequency, to allow detection of shortened and elongated pulses. Sampling should also away from expected transition points on the received signal. Assuming that 4 sample are taken per carrier period T_P, the samples should be taken at T_P/8, 3T_P/8, 5T_P/8, and 7T_P/8.

We have assumed that each transfer will begin with one or more start bits. The receiver will expect this start bit, and will assume that is has received this start bit. For instance, if the first start bit is a 1, the receiver will initially assume that the received bit is a 1. This will be the initial output of the demodulator.

If the receiver continues to receive regular patterns of square waves, the samples taken will be a regular pattern of 1100. As long as this pattern is maintained, no change in output from the demodulator will occur. If there is an [elongated/shortened] pulse, a transition from 1 to 0 has occurred. The output of the demodulator will change to 0, and sampling will continue.

While the output of the demodulator is 0, the 1100 pattern will be continued as long as there is no change in the data bit. The receiver will detect [elongated/shortened] pulses, and will trigger a change in output from 0 to 1 when it occurs.

This behavior can be described by a FSM. The input is the received signal, the output is the demodulated signal, and the clock is the sampling clock described above.
 
 

Note that the above diagram does not include transitions for unexpected transitions. Since we have synchronized the data bits with the rising edge of one of the carriers, it is expected that transitions will occur at this edge.

The FSM described by this state diagram can be easily converted to a VHDL design.

It was stated above that the carrier did not have to be duplicated at the receiver. A high speed clock at the receiver can be used to ensure that the sampling clock can be placed appropriately within the received waveform.

Thus, there is no need to consider phase differences between carriers. Because the local clock is running at a higher speed, the sampling pulses can be placed as required.

If there is a small difference in frequency between the transmitter and receiver, the sampling pulses will gradually move away from their intended locations within the received waveform. If they are to move past one of the transitions they are required to detect, the receiver will not function properly; it will detect a shortened or elongated pulse where none exists. However, for a sampling pulse to move past a transition point, it must be T_c/8 out of alignment. Within a typical 8 bit word with 1 start bit, the error in clock rate required to produce this misalignment is considerable, and well within the tolerance of modern clock circuitry.