Group Members: Norman Bo, Kelvin Leung, David Ritter

This document will describe a possible method of implementing an FIR (Finite Impulse Response) filter using an FPGA. The document will consist of a brief review of FIR topics covered in EE 438, and will then describe a practical implementation using an FPGA.

Introduction:

The filters discussed in this document will be discrete with respect to time and to signal amplitude. This is necessary for digital implementation.

An FIR filter can be defined as a filter whose output is determined by a weighted sum of past and present input values. Furthermore, the impulse response of an causal FIR filter must be 0 for all discrete times k < 0, as well as for times k > N, where N is some positive integer.

Eg.

The transfer function of this filter is:

The impulse response of the filter is then the finite sequence:

Filter Design using Windowing:

The windowing method of FIR filter design bases the filter impulse response sequence (and consequently, the filter transfer function), on the coefficients of the Fourier series expansion of the desired frequency response function. Since this series will be infinite, the series must be truncated. The means of truncation is a technique known as windowing. A variety of windows are available for use; these will be described later.

The process below can be used to create a FIR filter impulse response which is non-causal. A causal filter can be produced from this design by delaying the impulse response by an appropriate number of discrete time units.

The frequency response of the desired filter, H(e^jwT), can be related to the impulse response h(k), as follows:

where T is the sampling period.

Based on this equation, the desired impulse response h(k) can be determined.

This impulse response must then be truncated by multiplying h(k) by the window function w(k). The resulting impulse response, h?(k), determines the transfer function, H?(z), of the FIR filter.

In the simplest case, the windowing function is rectangular, ie. w(k) = 1 for |k|<(N-1)/2, and 0 elsewhere.

The rectangular window, however, does not produce the ideal frequency response. Use of a rectangular window introduces ripple to the frequency response of the filter. This ripple can be reduced by using a smooth window function. A variety of window functions have been developed. These windows are summarized below:
 

Window	Window Function (w(k)=0 for |k|>(N-1)/2
Rectangular	1
Hanning	0.5[1+cos(2p k/(N-1))]
Hamming	0.54+0.46cos(2p k/(N-1)
Blackman	0.42+0.5cos(2p k/(N-1)+0.08cos(4p k/(N-1)

Other window functions exist. Refer to the Bose, page 258, for more details

An example of the effects of the different windows on the FIR filter frequency response is shown in the following postscript files. The first figure shows the response of the filter designed using the rectangular window. The second figure shows the response of a filter designed using a Hamming window. The ripple seen in the first figure is largely removed by the use of the Hamming window

 rectangular window

 hamming window

Having obtained the coefficients that describe the impulse response, the filter can be designed in hardware. The simplest hardware implementation is a N-Tap filter. If the impulse response depends on N discrete input points, the filter can be implemented using a series of flip-flops,

The flip-flops store past samples of the input, which are then multiplied by the appropriate filter coefficient. All products are summed to give the filter output.

 The following VHDL code is a possible implementation of this design.

entity FIR is
generic(DATA_SIZE : integer := 8);
port(data_in: in std_logic_vector(DATA_SIZE-1 downto 0);
data_out: out std_logic_vector(DATA_SIZE-1 downto 0);
clock: in std_logic);
end entity FIR;

architecture behaviour of FIR is
signal d1,d2,d3 : std_logic_vector(DATA_SIZE-1 downto 0);
signal c1,c2,c3 : std_logic_vector(DATA_SIZE-1 downto 0);
begin

c1 <= "00000001";
c2 <= "00001111";

c3 <= "00001010";

d1 <= data_in;

clock_logic: process(clock)
begin
   d3 <= d2;
   d2 <= d1;
end process clock_logic;

data_out <= c1*d1 + c2*d2 + c3*d3;

end behaviour;

References:

http://screwdriver.bu.edu/cn760-lectures/l3/l3np/ppframe.htm

http://www.actel.com/appnotes/5192645.pdf

Bose, N.K. Digital Filters: Theory and Applications. North-Holland: New York, 1985.

Childers, Donald and Durling, Allen. Digital Filtering and Signal Processing. West Publishing Company: New York, 1975.