Figure Q1 and Figure Q2
Considerations For CMOS Interfacing
This application note is provided to help our fellow students in understanding and selecting interface elements for their projects. Three topics are discussed:
At the end of this note there is a short FAQ on Motorola CMOS parts. There are also a few tips on making measurements using an oscilloscope probe in high speed CMOS circuits taken from [1].
Three types of pre-packaged interface circuits will be presented: buffers, bus transceivers and latches. All three provide improved signal shape, increased signal current and a layer of electrostatic protection.
Buffers
Buffers are the simplest of logic elements they are unidirectional and t. They are very important in improving the shape of a signal, increasing the strength of the driving current and reducing the possibly of electrostatic discharge damaging the FPGA. Buffers allow signals to pass in one direction. Some buffers are output enabled so that the outputs can be placed in a high impedance state (Tri-state). A short list of CMOS buffers is presented in Table 1.
|
Device Number |
Function |
Output Enable |
I/O Pairs |
Pins |
|
Inverter |
No |
6 |
14 |
|
|
Schmitt Trigger inverter |
No |
6 |
14 |
|
|
Noninverting buffer |
Yes |
4 |
14 |
|
|
Inverting buffer |
Yes |
8 |
20 |
|
|
Noninverting buffer |
Yes |
8 |
20 |
Transceivers
Buffers are limited in that signals can only pass in one direction. Transceivers add more flexibility because they because they are bi-directional. An extra pin is included so that the direction of the transceiver can be determined. The output enable of these circuits will put all of the outputs into the high impedance state. A short list of transceivers is given in Table 2 below.
|
Device Number |
Function |
Direct Pin Compatibility |
Pins |
|
Octal 3-StateNoninverting Bus Transceiver |
LS |
20 |
|
|
Octal 3-State Inverting Bus Transceiver |
LS |
20 |
The bus transceiver acts as a bi-directional buffer. The DIR controls the direction of the data flow and the OE enables the output. Bus Transceivers can be used in order to buffer data in a digital system, which must be bi-directional, and is usually used on a data bus.
Latches
Latches are used for pipelining of your circuit. They take in the specified inputs, and based on the latch enable and output enable output, send the appropriate date to the output. A short list of CMOS latches is presented in Table 3.
|
Device Number |
Function |
Latch Enable |
Output Enable |
I/O Pairs |
Pins |
|
Dual 2-Bit Transparent Latch |
Y |
N |
2 |
16 |
|
|
8-BIT Addressable Latch/1-of-8 Decoder |
-- |
-- |
-- |
16 |
|
|
Octal 3-State Non-inverting Transparent Latch |
Y |
Y |
8 |
20 |
|
|
Octal 3-State Inverting Transparent Latch |
Y |
Y |
8 |
20 |
|
|
Octal 3-State Inverting Transparent Latch |
Y |
Y |
8 |
20 |
|
|
Octal 3-State Non-Inverting Transparent Latch |
Y |
Y |
8 |
20 |
A Way to Estimate Output Resistance
An easy way to obtain a worst case value for the output resistance of any CMOS driver is to divide the minimum high-level output voltage VOH (or the maximum low-level output voltage VOL) by the corresponding output current.
Example: The worst case output impedance for the CMOS 74HC245 is
RL = VOL/IOUT = 0.40V/0.006A = 67
WRH = (VCC-VOH)/IOUT = (4.5V-3.7V)/0.006A = 134
W
Affects of Loading on System Response
Loading occurs in both a resistive and capacitive sense. The effects of this loading degrade the system performance.
Example: One line on a data bus is connected to 5 74HC245 bus transceivers. The bus transceivers have a worst case 15 pf impedance each. Calculate the RC rise time
T63% = (5*15pf)(134
W ) = 10nsT90% = 2*T63% = 20ns
The propagation delay for 4.5V VCC is 22 ns. That means that the propagation delay is almost doubled due to presence of capacitive loading. This will make the circuit non-operational for a clock greater than 28 MHz.
Questions and Answers
What are Schmitt triggered inverters or what does that squished O in the middle of the inverted diagram mean?
Both of these things mean that the inverter is Schmitt triggered. Schmitt triggering improves noise immunity. It also allows the inverter to "square-up" signals. The hysteresis effect of the Schmitt-trigger is shown in figure Q1. Figure Q2 shows how a normal inverter works. It can be seen that if the normal inverter encounters noise around Vt there could be a lot or noise on the output. The Schmitt trigger works by raising the trigger point higher (it improves noise immunity).
Figure Q1 and Figure Q2
When and why is it important that some gates can be set into a high impedance state?
It is important if there are several outputs connected to the same wire. It is important because only one output should be able to drive that wire.
What is Tri-State?
It is when the output of the element in question is floating and electrically isolated from the rest of the circuit.
What is the difference between the HC245A and the HC640?
The MCHC245A is a non-inverting bus transceiver that uses two-way asynchronous communications for 2 way asynchronous communication between data buses.
The device has an active low Output Enable pin, which is used to place the I/O ports into high impedance states. The Direction control determines whether data flows from A to B or from B to A.
The MC640 is similar to the previous component, except it is an inverting bus transceiver.
How do I define inputs and outputs for transceivers?
It is important to note that within an IC all pins lines on either data port A or data port B must ALL be defined as inputs or outputs.
Why use a transceiver?
Bus transceivers are useful due to the fact that there is a low input current and has high immunity to noise. The bi-directional ability of transceivers allows ease of design across datalines.
What is the difference between transparent latches and addressable latches?
The difference between a transparent latch and an addressable latch is that an addressable latch acts more like an 8-bit multi-plexer (
See Data Sheet) while a transparent latch takes the inputs in and based on the latch enable and the output enable feeds those inputs to the output.What is the difference between MC54 and MC74?
There is no real difference between the MC54 prefix and the MC74 prefix, they are just prefixes used internally by the company.
Hints on Measuring High Speed Digital Circuits
Eventually you’ll have to debug at least a section of high speed digital logic. These rules will make things a little easier on you. The authors obtained these hints from [1]
1) Ground the measuring device as near to the point of measurement as possible – this means wrapping a curly-cue around the probe shielding and touching both the probe tip and the end of the ground wire to the signal and nearest ground respectively.
2) Find the probe with the least capacitance – less loading means better measurements. Setting the probes on times ten will usually reduce the capacitance.
3) View a serial data stream by triggering on the clock – God help you if you do not
4) If all else fails consider slowing the clock rate – a slow clock will allow transients to settle giving you a better chance to figure out what is going on.
References
[1] Johnson H., Graham M. "High-Speed Digital Design : A Handbook of Black Magic" Prentice Hall Inc, 1993
[2] Motorola : High Speed CMOS Data, 1996