This application note describes the implementation of a six digit, seven segment scanning display.

One of the main advantages of a scanning display is a significant reduction in the number of output lines required. Six seven segment display units would require 42 data lines if each display unit was wired individually (7 data lines/display unit * 6 display units = 42 data lines), in addition to the 6 enable lines which must be sent to each display unit.

In a scanning display, the seven segment data lines are shared between all six of the display units. The 6 enable lines are still required of course, for a total of 13 output lines. Compare this to the total of 48 lines required for a ‘regular’ display, and the advantages of a scanning display readily become apparent.

• The six digits to be displayed are input to the display module in BCD format
• The numbers are fed into a 6-to-1 mux
• Each of the six display units is enabled sequentially, and as each is enabled, the seven segment data required by it is converted from BCD format and output.

The display module has a local FSM which waits for a ‘startdisplay’ signal from the main system FSM. When ‘startdisplay’ is received, the local FSM loads the two 12-bit inputs into input registers. The outputs of these registers are fed into an 8-to-1 mux which is used to select the data for one BCD digit from the six.

The select lines for the mux come from a 3-bit counter, which counts from zero to five and then wraps around. (The counter wraps at five because only six digits need to be multiplexed, and only six display units need to be enabled.) The counter output also feeds into a 3-to-8 decoder, and the first six outputs of this decoder are used as enables for the six seven segment display units. This is done to synchronize the scanning display – when the counter is at "010" for example, the data for the third BCD digit (the MSB of the current speed) is selected for output by the MUX, and the third output of the decoder goes high (the rest are zero) so that the third seven segment unit is simultaneously enabled.

The enable outputs, and the display data lines are fed into output registers as a matter of good design methodology.

The local FSM plays an important part in synchronizing the display data output with the display unit enable outputs, in conjunction with the 3-bit counter. As the counter counts from "000" to "101", it sequentially enables the six display units, and simultaneously causes the correct display data to be multiplexed out onto the display data lines. When the FSM receives the ‘startdisplay’ signal, it waits for the 3-bit counter to hit "101" and then loads the input registers. This is to ensure that the entire display is scanned at least once before a change is allowed. After loading the input registers the first time, the FSM never waits for a ‘startdisplay’ signal to arrive again, it continuously loads the input registers and scans the display.

The inputs, as stated before are 6 BCD digits. The BCD digits have been divided into two input vectors, crnt_speed and set_speed, each of which have 3 BCD digits (i.e. they are each 12 bit vectors). Simply map as many of these digits as you require, and let the other inputs be tied to zero. When the data at the inputs is stable and you wish it to be displayed, send the ‘startdisplay’ signal high. The seven segment data corresponding to your inputs will arrive at the output shortly. Simply port map the seven segment data lines and the enable lines and you're done.