When using the lpm_ram_dq to access the memory on board, I found that it was most easily accomplished by synchronizing the input and output to the clock. By synchronizing the output to the clock, you can be sure of when the value presented on the output of the lpm_ram_dq is a valid and stable result. The drawback to synchronizing both the input and output to the clock is that every access to the RAM will take two clock cycles. This is because the output from the module will not be correct until one full clock cycle after the address was read in. The following waveform depicts how the lpm_ram_dq behaves:

Here is some sample code on how I generic and port mapped the lpm_ram_dq module when I created an instance of it:

The explanations of each of these signals and generics can be found in the Altera's Max+plus2 help manual or at this other student application notes . However, it did not explain that when inputting an address to the lpm, the address is automatically adjusted by the width of the data for you. For example, if the current address was 01 (binary), then to read the next element after you can simply increment the address by 1 to give you an address of 10 (binary) regardless of the width of the data. As well, when you wish to write to memory, the write enable signal must be high at the same edge where the address is read in.

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If there are any concerns about the content of this document, or if there are any errors, please e-mail me at pcchan@gpu.srv.ualberta.ca.