Here are several optimizing techniques that I discovered through the various labs. These may work for your circuit or then again, they may not. However, some these techniques helped me reduce the number of logic cells as well as increase the maximum clock frequency of my multiplier for lab 4.

Tip 1: When using a case statement for comparison, try moving the case that is most frequently accessed to the top. Then place the next most frequently used case after, and so on. For my multiplier, this swapping of case positions significantly reduced the number of logic cells occupied by the design (by about 3%). The maximum clock frequency was also slightly increased. As well, sometimes the order in which signals are assigned can make a small difference. This tip is mainly based on the fact that Max+plus2 is dependent upon how the VHDL code is written. By swapping several statements around, Max+plus2 will most likely layout the design differently and thus change the number of logic cells used and the delay of the circuit.

 Tip 2: Try to always use the same clock for all components in the design, as well as on the same edge. If using opposing edges for different parts, Max+plus2 assumes that they are two different clocks. As well, when I was designing my multiplier using both edges of the clock, the maximum clock frequency was almost half of the frequency of a similar design using only the rising edge.

 Tip 3: While not exactly an optimizing technique, I have come across this problem several times. If you have a process generating output that is being displayed slowly as a solid bar, this is most likely because the process is being executed time after time. Even if you have several signals in the sensitivity list of the process, I have witnessed that sometimes, processes do not react to the sensitivity list. In these cases, even if clock was the only signal in the sensitivity list, the process would execute all the time. What I had to do to fix this problem was make the process edge-triggered. Normally, this does not affect the design at all anyways. It was also mentioned that it is good practice to include the clock signal in the sensitivity list in Max+plus2, regardless of whether or not it is actually used in the process.

 Tip 4: If you are receiving error messages such as "Signal Input(3) has no source" this could be due to the fact that the signal Input is connected to another internal signal. While this other internal signal may have been initialized to a default value when you first declared the signal (ie: signal Input : std_logic_vector(3 downto 0) := (others=>'0') ), I have noticed that this default value is not always held by the signal. So if the internal signal is never tied to an output and only to inputs, then essentially you have nothing trying to drive an input. To get around this, place a concurrent statement in the architecture of the design assigning a value to that internal signal which is trying to drive the signal Input. 

 Tip 5: When using a counter, do not use integer types for signals or variables as these will be represented in 24 bits!! Instead, use a std_logic_vector with a width wide enough for your maximum value, or use a subset of the type integer. This can dramatically reduce the number of logic cells required in your design.  

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If there are any concerns about the content of this document, or if there are any errors, please e-mail me at pcchan@gpu.srv.ualberta.ca.