SEEQ 80220/80221 100BASE-TX/10BASE-T Ethernet Media Interface Adapter

SEEQ 80220/80221 100BASE-TX/10BASE-T Ethernet Media Interface Adapter

Introduction

This document contains a brief explanation regarding the 10 Mbps implementation of the SEEQ 80220/80221 Ethernet transceiver as a system interface. Specifically, this transceiver is ideal for decoding and extracting data from Ethernet packets that conform to the IEEE 802.3 (Ethernet) frame standard. Despite all of the wonderful features of this chip, only those features relevant to 10 Mbps reception will be discussed.

Description

The SEEQ 80220/80221 consists of the following:

4B5B/Manchseter encoder/decoder
scrambler/descrambler
100Base-TX/10Base-T twisted pair transmitter with wave shaping and output driver
100Base-TX/10Base-T twisted pair receiver with on chip equalizer and baseline wander correction
clock and data recovery
AutoNegotiation
Controller interface (MII)
Serial port (MI)

IC Chip Types

The 80220 and 80221 are different IC configurations of the same chip. The 80220 incorporates the design of the Ethernet transceiver in a 44 pin IC, while the 80221 uses a 64 pin. The 80221 has extra features that the 80220, due to pin limitations, does not implement. These extra features are mostly associated with 100Base-T4 implementation.

10Mbps Implementation and Pin configuration

The AutoNegotiation algorithm enables the 80220/80221 to automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation.
Eleven 16-bit internal registers can be controlled via the MI, but can be automatically initialized.
A twisted pair cable input circuit must be implemented, which consists of a resistor network and several isolation transformers. This is to allow data transfer between the RJ45 connection and the 80220/80221 chip.

A 25 MHz clock input is necessary to generate the receive clocks (RX_CLK) on the chip, which is reduced to 2.5 MHz on the output.
When no data is present, carrier sense (CRS) and receive data valid (RX_DV) are low.
When data is detected, CRS and RX_DV are asserted on the falling edge of RX_CLK.
Also accompanying each falling edge of the RX_CLK output from the chip is a data nibble (RXD[3:0]).
The first 16 nibbles contain the preamble and start-of-frame-deliminator (sfd) of the Ethernet packet. This information is used primarily by the transceiver.
The 17^th nibble contains the first four bits of the packet-encapsulated data.

Thus the system that uses this Ethernet interface should be concerned with the nibbles RXD[3:0] being output on the falling edge of each RX_CLK pulse.

This image has been copied fomr the SEEQ 80220/80221 100BASE-TX/10BASE-T Ethernet Media Interface Adapter.

For more detailed descriptions and device specifications, visit http://www.seeq.com .

Submitted by:

Jeffery Lo

Last Updated:

06/10/98

Edward Shen

Submitted by:	Jeffery Lo	Last Updated:	06/10/98
	Edward Shen