A Helpful Tip on using Tri-State
Altera has a tri-state module all ready for you to use. The component name is TRI and can be declared using:
component Tri
port (a_in : in std_logic;
oe : in std_logic;
a_out : out std_logic
);
end component;
|
Signal Name |
Type |
Function |
|
a_in |
std_logic |
Input value to tri-state buffer |
|
oe |
std_logic |
Tri-state output enable. 0 : a_out = Z 1: a_out = a_in |
|
a_out |
std_logic |
Output from tri-state buffer |
Hint: The output of the tri-state buffer can only be mapped to a bi-directional pin such as an "inout" pin. However, if you do not require the pin to be bi-directional but only as an output, you can map the output of the buffer to an internal signal first, and assign that internal signal to the output of the design. However, if you simply map the output of the tristate to the output of your design, Max+plus2 will complain. For example, the following will generate an error:
entity test is
port (input : in std_logic;
enable : in std_logic;
output : out std_logic
);
end entity test;
architecture mixed of test is
component Tri
port (a_in : in std_logic;
oe : in std_logic;
a_out : out std_logic<>
);
end component;
begin
buffer : Tri port map (
a_in => input,
oe => enable,
a_out => output
);
end architecture mixed;
As stated above, Max+plus2 will not allow the output of the tri-state buffer to be directly connected to an output pin on your design. The following code demonstrates how an internal signal can be used to have your device output tri-state values without making the pin bi-directional.
entity test is
port (input : in std_logic;
enable : in std_logic;
output : out std_logic
);
end entity test;
architecture mixed of test is
signal bridge : std_logic := '0';
component Tri
port (a_in : in std_logic;
oe : in std_logic;
a_out : out std_logic
);
end component;
begin
buffer : Tri port map (
a_in => input,
oe => enable,
a_out => bridge
);
output <= bridge;
end architecture mixed;
Author:
Patrick Chan (pcchan@gpu.srv.ualberta.ca)
364305
Co-Authors:
Neil Fraser 252885
Srilata Kammila 253698
Edmund Quan 244667
If there are any concerns about the content of this document, or if there are any errors, please e-mail me at
pcchan@gpu.srv.ualberta.ca.