-- Neil Fraser
-- 4-bit Random Number Generator

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity randomnumber is
port( enable,clock, reset, mode : in std_logic;
	  invect : in std_logic_vector(3 downto 0);
	  number : buffer std_logic_vector(3 downto 0)
	);
end randomnumber;

architecture behavioural of randomnumber is

component flipflop4 is
	port(	clock, reset,mode : in std_logic;
			d,a : in std_logic;
			q : out std_logic
		);
end component;

component xorfunc is
	port(	a,b : in std_logic;
			c : out std_logic
		);
end component;

signal e,f,g,toa,tob : std_logic;
 

begin

S0 : component flipflop4
port map	( 	clock => clock,
				a => invect(3),
				mode => mode,
		 		reset => reset,
		 		d => tob,         		-- source = q3
		 		q => toa			--goes to a of xor
			);
xor1 : component xorfunc
port map (	a => toa,
			b => tob,
			c => e
		);


S1 : component flipflop4
port map	(	clock => clock,
				a => invect(2),
				mode => mode,
				reset => reset,
				d => e,				-- source output of xor
				q => f				-- goes to d of S2
			);

S2 : component flipflop4
port map 	(	clock => clock,
				a => invect(1),
				mode => mode,
				reset => reset,
				d => f,				-- source = q or s1
				q => g				-- goes to d of s3
			);

S3 : component flipflop4
port map	(	clock => clock,
				a => invect(0),
				mode => mode,
				reset => reset,
				d => g,				-- source = q of s2
				q => tob				-- goes to d of s0 and b of xor
			);

assign : process(reset,enable)
begin		
	if rising_edge(enable) then
		number <= tob & e & f & g;
	end if;
end process assign;
end behavioural;