Address decoding in VHDL is fundamental to many designs especially those concerned with memory locations and value searching. Traditionally, a case-when command is used to compare an address value with a table, until the value is found. This is accomplished in a process, which executes the commands sequentially. By using an array of cascaded AND gates, it is possible, not only to increase the speed at which the decoding occurs, but also the total number of logic cells used.

The basic idea of an AND gate Decoder was presented in class (for those of you who missed that lecture). Below is the schematic concept with the truth table for a 4-bit decoder designed to detect the value 0101.

From this example, it can be seen that due to the properties of the AND operation, only when all four inputs are 1, will the output become 1, thus detecting the presence of this address.

The VHDL code to create this design can be viewed here. It is implemented for a four-bit address only, using the Altera software. For longer addresses, the separate AND gate files would have to be modified for an extra input signal.

A sample of the case-when statement decoding is included as well.

Initially, a single four-input component was created and then modified, to detect each address, in a higher level entitiy. However, Altera, during compilation of this higher level code, indicated that there was multiple sources for each four-input AND gate component. This compilation error, led to the creation of the sixteen different four-input AND gates to solve this problem.

Using the Altera software, this entity uses one logic cell to implement the design. In VHDL, there is a megafunction known as lpm_and, which enables the user to create a very large number of AND gates, with several inputs. This method also uses one logic cell per AND gate created.

When sixteen of these AND gates, each specifically programmed for each of the addresses 0000 to 1111, are employed as an address decoder, only sixteen logic cells are required. When the same decode algorithm is created using a case-when statement, with sixteen when conditions, is employed, it requires twenty-two logic cells. Therefore, by coding the specific hardware, six logic cells can be saved. For large-scale designs, using several stages of decoding, these saving would add up.

Also, the delay from input to output is faster for the four-input AND gate decoding. The average delay for this design is approximately 20 ns. Using the case-when decoding method, the delay from input to output is approximately 24.5 ns. Thus, several instances of this algorithm in a design, would contribute to a significant delay, if even two decoding stages are used.

Since, the Altera FPGA has a limited number of logic cells (1152) available, for very large designs, the ability to save several logic cells will allow the Altera optimization program more options, when implementing the VHDL code into hardware components. The need to increase the speed in a design, is also crucial. Although, four and a half nanoseconds is not a significant amount of time, its propagation through a design, can cause serious consequences.

Submitted by: Jeffery Lo (ID# 355679) and Edward Shen (ID#353566)