--ROM code
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
entity ROMTest is
GENERIC (LPM_WIDTH : positive:= 8;
LPM_WIDTHAD : positive:= 8);
PORT (address: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
inclock: IN STD_LOGIC;
outclock: IN STD_LOGIC;
memenab: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
end ROMTest;
architecture mixed of ROMTest is
begin
StartROM : lpm_rom
GENERIC MAP (LPM_WIDTH => LPM_WIDTH,
LPM_WIDTHAD => LPM_WIDTHAD,
LPM_TYPE => "L_ROM",
LPM_FILE => "ROMTest.mif") -- note remember to call this initialization file the same as the original file
PORT MAP (address => address,
inclock => inclock,
outclock => outclock,
memenab => memenab,
q => q);
end mixed;