HD44780, HD44780A (LCD-II)

(Dot Matrix Liquid Crystal Display Controller & Driver)

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Description

Pin Description

Function of each Block

The HD44780 has two 8-bit registers, an instruction register (IR), and a data register(DR).
The IR stores instruction codes such as display clear and cursor shift, and address information for display data RAM (DD RAM) and character generator RAM (CG RAM).
The DR temporarily stores data to be written into the DD RAM or the CG RAM and the data to be read out from DD RAM or CG RAM. Data written into the DR from the FPGA is automatically written into the DD RAM or the CG RAM by internal operation. The DR is also used for data storage when reading data is read from the DD RAM or the CG RAM.
 

Busy flag (BF)

When the busy flag is 1, the HD44780 is in the internal operation mode, and the next instruction will not be accepted. The busy flag is output to DB7 when RS = 0 and R/W = 1. The next instruction must be written after ensuring that the busy flag is 0.
 

Address Counter (AC)

The address counter (AC) assigns addresses to DD and CG RAMs. When an instruction for address is written in IR, the address information is sent from IR to AC. After writing into ( or reading from) DD or CG RAM display data, AC is automatically incremented by 1 of decremented by 1. AC contents are output to DB0-DB6 when RS = 0 and R/W = 1.
 

Display data RAM (DD RAM)

The display data RAM (DD RAM) stores display data represented in 8-bit character codes. Its capacity is 80*8 bits, or 80 characters. The DD RAM address (Add) is set in the address counter (AC) and is represented in hexadecimal.
 

Character Generator RAM (CG RAM)

In the character generator RAM, the user can rewrite character patterns by program. With 5*7 dots, 8 character patterns can be written and with 5*10 dots, 4 characters can be written.
 

Register Selection

RS	R/W	Operation
0	0	IR write as internal operation (Display clear, etc.)
0	1	Read busy flag (DB7) and address counter (DB0-DB6)
1	0	DR write as internal operation (DR to DD or CG RAM)
1	1	DR read as internal operation (DD or CG RAM to DR)

 

Connection for LCD Contrast

Instructions

VHDL example for LCD display Initialization

Notes:

• After power on, the LCD has to wait more than 15 ms for Vcc rises to 4.5V before accepting the first instruction.

• I set signal "count" count from 0 to 3. However, this value is depend on the system clock. Make sure the LCD has enough time to execute the next instruction. Execution time for each instruction can be found in the Instructions table.

--lcd_init.vhd This program initialize the LCD display

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity lcd_init is

     generic(width : positive := 8);
     port(reset, clock, enable, done_ack : in std_logic;
              done, RW, rs, lcd_e : out std_logic;
              Qout : buffer std_logic_vector(width-1 downto 0)
             );

end lcd_init;

architecture initial of lcd_init is

    type state_type is (waiting, i0, i1, i2, i3, donestate);
    signal state, next_state : state_type;
    signal count,count_temp : std_logic_vector(1 downto 0);
    signal Qout_temp : std_logic_vector(width-1 downto 0);

begin

running : process(state,enable,done_ack,count) is

begin

case state is

when waiting =>
     done <= '0';
     lcd_e <= '1';
     RW <= '0';
     rs <= '0';
     Qout_temp <= "00000000";

     if enable = '1' then
          next_state <= i0;
     else
          next_state <= waiting;
     end if;

when i0 =>
     Qout_temp <= "00000001"; --clear display

     if count = "11" then
          next_state <= i1;
     else
          next_state <= i0;
     end if;

when i1 =>
     Qout_temp <= "00000010"; --clear display & returns cursor to HOME (top left)
 
     if count = "11" then
          next_state <= i2;
     else
          next_state <= i1;
     end if;

when i2 =>
     Qout_temp <= "00111000"; --2 line display
 
     if count = "11" then
          next_state <= i3;
     else
          next_state <= i2;
     end if;
 

when i3 =>
     Qout_temp <= "00001110"; --truns on display with cursor at home position
 
     if count = "11" then
          next_state <= donestate;
     else
          next_state <= i3;
     end if;

when donestate =>
     done <= '1';
     Qout_temp <= ( others => '0' );

     if done_ack = '1' then
          next_state <= waiting;
     else
          next_state <= donestate;
     end if;

end case;

end process running;

timing : process(clock,reset) is

begin

    if rising_edge(clock) then
         Qout <= Qout_temp;
         count <= count_temp;
             if reset = '1' then
                  state <= waiting;
                  count_temp <= "00";
             else
                  state <= next_state;
                  count_temp <= count_temp + "01";
             end if;
    end if;

end process timing;

end initial;

Last update: October 27, 1998