Non-Zero Array Index Bug

Synopsis

When using arrays across ports which have a non-zero lower range value, the compiler connects up things wrong. This affects Maxplus2 versions 8.1.9 and 7.2.1.

Details

This bug manifests itself when using arrays across port boundaries and it can be most easily demonstrated with these three files:

params.vhd - declare a type which is an array starting at one:

-- parameters for bug2  Rob Chapman Mar 28, 1998

Library IEEE;
use IEEE.STD_Logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

-- parameterize the network
package params is

  constant N : positive := 14;  -- number of neuroprocessors

  subtype achoice is natural range 0 to N;

  type choices is array (natural range 1 to N) of achoice;

end package;

bug2a.vhd - create a component with the array in the port and assign default values:

-- Bug # 2 in Altera Maxplus2 compiler  Rob Chapman  Mar 27, 1998

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

use work.params.all;

entity bug2a is
  port( a : out choices );
end entity;

architecture test of bug2a is
  begin
    
    thebus : for i in 1 to N generate
      a(i) <= i;
    end generate;
  
end architecture;

bug2b.vhd - instantiate the component and connect up to it using a signal as the intermediate:

-- Bug # 2 in Altera Maxplus2 compiler  Rob Chapman  Mar 28, 1998

Library IEEE;
use IEEE.STD_Logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

use work.fixparams.all;

entity fixbug2b is
  port( c : out choices);
end entity;

architecture test of fixbug2b is
  component fixbug2a
    port( a : out choices );
  end component;

  signal b : choices;

begin
    
    alabel : fixbug2a
      port map ( a => b );

    c <= b;
  
end architecture;

While this is valid VHDL code, the Maxplus2 compiler connects up the arrays wrong and as a result the following error messages are created:

Error: Can't find a pin in the design file that corresponds to pinstub/port 'a0_ 3' in the symbol, Function Prototype, or other construct 'alabel' that represents the file

Error: Can't find a pin in the design file that corresponds to pinstub/port 'a0_ 2' in the symbol, Function Prototype, or other construct 'alabel' that represents the file

Error: Can't find a pin in the design file that corresponds to pinstub/port 'a0_ 1' in the symbol, Function Prototype, or other construct 'alabel' that represents the file

Error: Can't find a pin in the design file that corresponds to pinstub/port 'a0_ 0' in the symbol, Function Prototype, or other construct 'alabel' that represents the file

Fixes

There are two way to work around this bug:

• shift indexing to be zero based
• add elements down to zero

Shifting Indexing to be Zero Based

This uses the same number of array elements and the above code can be made to compile properly by making the following changes. First the type must be changed in params.vhd:

type choices is array (natural range 0 to N-1) of achoice;

And secondly, any place where the indexing is exposed, must be modified as well. In the above code, this only affects one statement in bug2a.vhd:

thebus : for i in 0 to N-1 generate

Add elements down to zero

This uses an extra array element. First the type must be changed in params.vhd:

type choices is array (natural range 0 to N) of achoice;

Secondly, any place where an array is assigned, the added elements must assigned. In the above code, this adds only one statement in bug2a.vhd:

a(0) <= 0;

This page was updated on April 3, 1998. For a human interface, contact Rob Chapman