When using using negative numbers, do not use the concurrent case statement to do the assignment because it ignores the sign. Instead use the process statement assignment. This affects Maxplus2 versions 8.1.9 and 7.2.1.
This bug manifests itself when using the concurrent case statement to do an assignment of a negative number to a signal. It seems that the sign is lost. Instead, the equivelant process case statement can be used. It is a little more verbose and is less preferred for code maintenance, but it works. Both equivelant VHDL statements are presented in the following VHDL file:
bug1.vhd - problems with negative number assignment and the concurrent case statement:
-- Altera bug: "with...select..." Rob Chapman Mar 9, 1998
-- Statement B works. Statement A produces 1 instead of -1 for the
-- assignment to w1 when np1 is 2.
Library IEEE;
use IEEE.STD_Logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity bug1 is
port(np1, np2 : in integer range 0 to 3;
w1, w2 : out integer range -1 to 1);
end entity bug1;
architecture truth_table of bug1 is
begin
-- statement A
with np1 select
w1 <= 1 when 1,
-1 when 2,
0 when others;
-- statement B
process(np2)
begin
case np2 is
when 1 => w2 <= 1;
when 2 => w2 <= -1;
when others => w2 <= 0;
end case;
end process;
end architecture truth_table;
When this code is compiled and run, the following waveform is produced:
Clearly, in the interval 2, the values for w1 and w2 are different. Since the precision of the numbers is 2 bits, 11 in binary is -1 in decimal. For w1 the value is just 1. Whereas w2 has the proper assigned value from the process statement, 11.
This page was updated on April 3, 1998. For a human interface, contact
Rob Chapman