External memory is a necessity when relatively large amounts of storage are required by the FPGA application. For a "medium-sized" amount of memory, perhaps in the range of 8 kilobytes to 1 Megabyte, static ram (SRAM) may be the designer's first choice. The main advantage of SRAM is that it is the easiest to interface to and maintain. SRAMs generally have a direct, non-multiplexed interface for addressing memory, and only require a constant DC supply in order to retain data. In the case of CMOS static memories, this power requirement is extremely small, allowing the implementation of reliable non-volatile battery-backed systems.

SRAM Operation

The operation of SRAM is generally similar to the "IO-RAM" LPM used to implement internal memory on the Altera FLEX device. The data port is bi-directional, and it's behaviour is determined by the level of it's Output Enable (OE*) input.

ONE IMPORTANT OBSERVATION to note is that Altera's LPMs generally use positive logic, and most SRAMs use negative logic. Thus, a low signal on OE* causes the data bus to act as an output, on WE* causes a write operation, and on CS* enables the chip (CS* is Chip Select, and is equivalent to memenab on an lpm_ram_io component).

The device can be used "asynchronously" so long as the timing parameters are adhered to, as the IO on an SRAM is not "registered". It is recommended, however, that a "synchronous" read or write be done (based on the system clock) that ensures timing requrements are met. Typical parameters for a high-speed SRAM are given in this data sheet from Alliance Semiconductor, along with more in-depth timing diagrams.