Minimialistic Approach to Design:
Shrinking the size of the IALU
Noah Aklilu <aklilu@ee.ualberta.ca> <http://www.ee.ualberta.ca/~aklilu/>
For our group project, a complex number calculator, we had to design a ALU that was capable of handling complex numbers. When we initially designed our system, we had separate paths to perform addition, subtraction and multiplication. Our ALU ended up taking 82% of the Altera chip. Not good because we still had to fit the rest of the project on the chip.
Our solution was to minimize our datapath to the point that we had only one multiplier and one adder/subtracter block as our principal blocks, with latches to hold initial, intermediate and final values. This reduced the ALU to 36%, a much more manageable size. With the reduced size, also came increased clock frequency we went from running at ~8MHz to ~24MHz.
This does result in an increase in the size of the control path, but it is insignificant compared to the chip area gained from the data path.
Look at the equations that were required:
Addition : (A + Bi)+(C+Di) = (A+C) +(B+D)i
Subtraction: (A+Bi)-(C+Di) = (A-C) + (B-D)i
Multiplication : (A+Bi)(C+Di) = (AC-BD) + (AD+BC)i
For each equation, the operations can be done serially and stored in latches, and latched values can be switched using multiplexers to connect them to either the multiplier or the adder/subtracter.
For Example: Addition
Of course for multiplication this gets a little more complex. To hold the intermediate values AC, BD, AD, BC, two latches are used. Since only AC and BD or AD and BC can occur at a time, no more than two latches are needed. For the really brave at heart, you can pipeline the multiplier and reduce your clock frequency. We went with a 3-stage pipelined multiplier.
The based components used in the VHDL code were built around Altera's LPMs, the components could be swapped for pure VHDL code. The decision to go with LPMs was made since we already had to do our development on Maxplus2, no reason to invent the wheel twice.
