Using a bi-directional data bus requires special in and out buffering.

This buffering enables the inout port to act as only one of an input port or an output port at a time. There is a control line that enables the user to decide if the inout port is in input or output mode.

The way that this control works is demonstrated when it is tied to Vcc and ground, in turn, and the optimizer is allowed to change the IOBUF.

For Example:

(Note: inout_por should read inout_port. Input and output are internal, and for the names to make sense, should be considered as input to outside and output from outside.)

The above picture shows the I/O buffer (the two triangles pointed in opposite directions) with the control line tied to logic 1 and other assorted buffer and port signals. The following, which is a copy of the logic trimming report explains what happens.

Due to VCC signal on pin 'T' of OBUFT symbol 'U10/B':

Logically reduced OBUFT symbol 'U10/B' removed.

Loadless signal 'n6' removed.

Unused pin 'O' on IBUF symbol 'U11' removed.

Disabled IBUF symbol 'U11' removed.

Unused signal 'input' removed.

The end result is that the input port is ignored, and whatever appears on inout_port appears directly on the output port.

If a similar experiment is performed with the control line tied to logic 0 the following trimming report results:

Grounded input pin 'T' on OBUF symbol 'U10/B' removed.

OBUFT symbol 'U10/B' changed to OBUF.

This means that the tristate part of the I/O buffer is reduced to a simple output buffer. Therefore, whatever appears on the input port is carried directly to both the output port and the inout port.

To get Synopsys to use this buffer, you must include it in your VHDL code as in the following example.

-- inout_driver.vhd

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

ENTITY in_out IS

PORT(

inout_port : inout STD_LOGIC;

control : in STD_LOGIC;

input : in STD_LOGIC;

output : out STD_LOGIC

);

END in_out;

ARCHITECTURE BEHAVIOUR OF in_out IS

component IOBUF

port(O: out std_logic;

IO: inout std_logic;

I: in std_logic;

T :in std_logic);

end component;

BEGIN

temp <= '0';

A0 : IOBUF port map(O => output,

IO => inout_port,

I => input,

T => control);

END behaviour;

When attempting to compile under Synopsys, there are a couple of different commands needed.

Just before assigning pin numbers to ports, give the command

Set_don’t_touch find (cell, {A0} –hierarchy) true

(see below for explanation of A0)

And, just before "replace_fpga", issue the command:

Set_don’t_touch find (cell, {A0} –hierarchy) false

Where A0 is the instance name or names of your IOBUFs. (i.e. {A0} or {A0 A1 buffer} etc. Remember that this is case sensitive.)

Another command that can be useful in compiling VHDL under Synopsys is used when specifying that a signal is to have clock buffering.

After your set_port_is_pad commands, give the command:

Set_pad_type –exact BUFGP_F clock

Where clock is the signal name you want the buffering applied to. This is the fix to the errors where xmake tells you it expects a BUFGP on a given signal.