-- 30 bit synchronous counter

--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity count30 is
	port(Enable, clr, Clock : in std_logic;
		Q : out std_logic_vector(29 downto 0));
			
	end count30;
	
architecture behaviour of count30 is


begin

       counter: process 
      variable count :std_logic_vector(29 downto 0);
       
       begin
        
           wait until ( Clock'event and clock = '1' );
                if clr = '1' then 
                     count := "000000000000000000000000000000";
                elsif (Enable = '1') then
                     count:= count + '1';
                end if;
		Q <= count;
       end process counter;          

end behaviour;



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity  simple_counter is
	port(Clock: in std_logic;
	num: out std_logic_vector(29 downto 0));
			
	end simple_counter;
	
  	
architecture instance of simple_counter is


component count30
  port (Enable, clr, Clock : in std_logic;
		Q : out std_logic_vector(29 downto 0));
end component;
 signal temp1,temp0:  std_logic;

begin

  temp1 <= '1';
  temp0 <= '0';

 count: count30 port map (
             Enable  => temp1,
             clr  => temp0,
             Clock => clock,
             Q => num);
 
 
 
end instance;


-- code copied from ee 552 class notes sept 97 from Prof. Duncan Elliott
-- modified by Ray Still and Shazia Mardhani