NAMES: RAY STILL AND SHAZIA MARDHANI ACKNOWLEDGEMENTS: DUNCAN ELLIOTT & NORMAN JANTZ TITLE: IMPLEMENTATION OF 30-BIT COUNTER USING THE RAPID PROTOTYPING BOARD CAUTION: BEFORE USING THIS EXAMPLE TO IMPLEMENT YOUR OWN PROJECT, READ ALL OF ----------------------------------------------------------------------------- THE INSTRUCTIONS, AND THE WARNINGS AND ENVIRONMENT INFORMATION SECTION. ----------------------------------------------------------------------- FORMAT ------ shellprompt > is what you see when you call-up a terminal window before you type anything in it design_analyzer> is another type of prompt, (within the design analyzer) and should never be typed. Type only what follows it. RPB = Rapid Prototyping Board menu1 => command... menu1 => menu 2 => command... mean from menu1 select what follows the => symbol. If the next thing has ellipsis (...) following it, a dialog box will be called up. if what you select has an arrow after it, another menu will be brought up. [ ] indicates explanatory comments and won't be found on the screen, nor should they be typed or selected anywhere. ___ | | |__ indicates notes that teach more about a particular subject, but don't directly affect this example. FILES USED ---------- counter.vhd , fpga2.vhd , fpga2.script , ioplace1.script Rapid Prototyping Board introduction (very simplified) ----------------------------------------------------- The rapid prototyping board consists of a MC68306 microprocessor, various ports and buses, 4 switches, a bank of 16 Leds, Ram and Rom, and 2 Xillinx XC4010 Field Programmable Gate Arrays (FPGA). FPGA ANALYZER: ------------- 1. Go to the directory containing the vhdl program. In our case, shellprompt > cd ~/vhdl shellprompt > mkdir Xilinx 2. Now, on the shell prompt start design analyzer by typing the following command: shellprompt > fpga_analyzer & The Design Analyzer shell will be displayed on your screen. All the commands that we run from menus in Design Analyzer, may also be run from the command line . 3. It should be noted that the first step when reading a new design in Synopsys environment is to analyze each instance of the design. Analysis must take place starting with the lowest instance of hierarchy first, followed by each successively higher level. When this process is completed, only the top level of hierarchy is needed to elaborate. 4. Before you could actually read the design in Design_Analyzer, you might want to see the commands invoked by READ script. You can see these commands by starting up the command window. In order to do this, execute the following pulldown menu options: Setup => Command Window... The Command Window will pop up on the screen and you can use the scroll bar to move up and down to see various commands executed by Design Analyzer menu picks or custom scripts. You can also enter commands in the box followed by " design_analyzer> " prompt. 5. In order to read the commands in Design _analyzer, invoke the following pulldown menu choices: File => Analyze... [click on desired design. be sure to click on create library if it doesn't exist] File => Elaborate... [click on work, select desired design] 6. The fixed architecture of the FPGA requires us to specify which ports are going to use the input buffers, output buffers, clock buffers, etc. For this reason, we need to insert pads to our inputs, outputs and Clock. There are two ways to insert pads i.e one through the Command window and other through the menu options in the design_ analyzer window. We will discuss both approaches briefly. Menu Driven Approach: First of all, we need to select the port where we want to insert a pad (i.e I/O port). In order to select a port, we will first go to the symbol or schematic view. Now, select a port by clicking the left mouse button on it, or select multiple ports at the same time by drawing a box around (or through) all the ports you want to select. After that, go to the menu selection: Attributes => Optimization Directives => Input Pad This will bring up the "Input Port Attribute" window. Now, click the "Port is Pad" in order to make sure that this is where we want our pads to be inserted and then say "Apply". This will make "port_is_pad" attribute set on all the selected ports. a similar thing can be done for the output ports (with a slight twist) by choosing the output ports, and then selecting: Attributes => Optimization Directives => Output Pad this brings up 2 windows one labeled "Bus Selector" and the other labeled "Output Port Attributes". In our case, we have a 30 bit wide bus but only 12 leds, so we want to connect the 12 most significant bits to the leds and leave the other 18 bits disconnected. So, highlight the 12 ports with the highest numbers, and then go to the "Output Port Attributes" window, and select: Port is Pad then, reselect the output port and reselect: Attributes => Optimization Directives => Output Pad this time, highlight the 18 ports with the lowest numbers,and then go to the "Output Port Attributes" window, and select: unconnected At this point, you will see a block diagram in the design_analyzer window. The boxes in the diagram represent various levels of hierarchy in our design. If you wish to see different views of design, go to the down arrow on the left hand side of your Design_Architect window and click on it. Now, this view that is seen here, is like the entity in your program i.e a black box. The previous view was the "symbol view" and the symbol view is the current view. On the left hand side of the Analyzer window, there are a few more symbols. The first one is for hierarchical view, and the third one is for schematic view. The up arrow icon on the Analyzer window, will always bring you back to the top-level hierarchical view. ___ | [THIS SECTION IS FOR INFORMATION ONLY, and as such is totally optional) | | Script and Command Line Driven Approach: (the design has changed since | the script was written, so don't use this method now) | | to use the script, select: | | Setup > Execute Script... | | The Execute File window will appear on the screen and from there you | can choose the appropriate directory names to reach the appropriate | directory containing the .script file. After clicking on the | directory, double click on the .script file and click on o.k. | (Our file eg.script is added in the appendix.) | | (the script doesn't leave part of the output unconnected.) | (the command window shows a command line version of everything, and | the commands that appear in this window can be placed in a script | to enable automation of tasks, or you can memorize the commands, and | simply type them.) | | If you want all ports to be made into pads, and if you want to use the | command Line approach, go to Command Window and type: | | design_analyzer> set_port_is_pad "*" | | This one command, will find all the ports in your current design and | will set their attributes as "pad". |__ Design Analyzer, automatically inserts special buffering on signals such as clock, reset or clear, etc., But, we do not want this buffering to be inserted for the clock so, use the following command: design_analyzer> set_pad_type -no_clock Clock It is important to note that you should use the name for Clock that is used in your code. Now, since all the pads are set, you can use the Xilinx library and insert the pads into your design by typing the following command in the Command Window: design_analyzer> insert_pads now, if you open the schematic view of your design, you will find that the ports have been inserted. You should find yourself in the symbol view. If not, you can select the instance and click on the down arrow. In order to switch to the schematic view, click on the gate symbol on the left hand side of the design analyzer window. ___ | (optional) | If you select any of the large boxes and zoom in, you will see that | they are the library part iob_400. For zooming in, go to the menu bar | and select: | | | View => Zoom_in | | | and to Zoom out, | | | View => Zoom_out |___ 7. After you are done with inserting the pads, your next step should be to define their physical location on FPGA's. The example ioplace1.script is attached. one representative line is included here for the discussion that follows. set_attribute {"num[6]"} "pad_location" -type string "A9" The purpose of the set attribute command is to set the attribute "pad_location" to a pin name. That is, the signal named within {} is attached to the pin named by the letter number combination. In the example above, the signal clock is associated with the V5 pin of FPGA1. (see pages 73 through 82 of the RPB manual for a further explanation of what pins connect to where.) All of these commands could be typed individually from the command line, but it is quicker to use this script, so to execute this script, from the menu bar select: Setup => Execute Script... The Execute File window will appear. Select ioplace1.script and click on OK. 8. The next step is to compile our design so that we can convert our Synopsys format to technology-specific circuit description. In order to do that, go to the Command Window and type: design_analyzer> compile When the design is compiled, you will see that the schematic representation contains only CLBs (Complex Logic Blocks) and IOBs (Input Output Blocks) at the lowest levels of the hierarchy. You can descend through the hierarchy by double clicking on the instance and that should generate the schematic view of that instance. 9. Now, we need to convert the programmable cells in our design to Xilinx gate primitives. That can be done by the following command from the Command Window: design_analyzer> replace_fpga After executing this command, you should be able to see gate symbols instead of square boxes as before. The previous representation is not lost and will be included in .sxnf file that will be produced later. Our next step is to set the attribute for the part "Xilinx chip 4010pg191-6". (this is basically a part number and is written on the fpga case) For that purpose, we will type the following command in the Command Window: design_analyzer> set_attribute simple_counter "part" -type string "4010pg191-6" [this is all one command and must appear on the same line] Because Xilinx does not allow writing block names to the .sxnf file, we will run the following command on the command line : design_analyzer > set_attribute find(design, "*") "xnfout_use_blknames" -type boolean false [this is all one command and must appear on the same line] Our design is ready to be saved as .sxnf file and is ready for compilation with XACT software. Go to: File => Save As... The Save File dialog box will appear and in the File Name box, type: Xilinx/fpga1.sxnf (and do not hit the return key yet) Now, click on the bar next to File Format: and select XNF. Make sure that the "Save All Designs in Hierarchy" box is activated(shaded). And, click OK now. The Synopsys portion of the lab for the first Rapid Prototyping Board FPGA is completed and will now be referred to as FPGA1. 10. The RPB is designed such that the microprocessor has all the connections to FPGA1 but all except two LEDs are connected to FPGA2. In order to have connections between FPGA1 and the LEDs, we put logic in FPGA1 and use FPGA2 for the connection (our example is so small that FPGA2 is not needed, but in a larger project, FPGA2 could contain real logic as well). A sample design of FPGA2 is attached. (note the line containing the absolute pathname is this scripts location, and should probably be removed. In order to run the script, click on: Setup => Execute Script.... now select FPGA2.script file in the Execute File box. Click on OK. If there are any errors, in the script, the script will be halted and you will be asked if you still want to continue. All this can be seen in the Command Window. When the script has been completed, the Synopsys portion of the lab is finished and you can close the Design Analyzer and Command Window. 11. Change your directory to the Xilinx directory. shellprompt > cd Xilinx (this directory was made previously.) Now, in order to compile the .xnf file to bit file, execute the following command on shell prompt: shellprompt > xmake fpga1.sxnf Repeat the same command for fpga2.sxnf file. ie. shellprompt > xmake fpga2.sxnf After the compilation of both of these files you should be able to see fpga1.bit and fpga2.bit files. Now, we want to transform these two bit files into one Exormax(S-record) format file which will be transmitted to the RPB. On shell prompt, type the following command: shellprompt > makeprom -s 256 -f exo -o rpb -u 0 fpga1.bit fpga2.bit ___ | The command line arguments are as follows: | | . -s is the argument for the size of PROM in kilobytes. | | . -f is the format argument and exo represents the exormax (S-Record) | format. | | .-o argument is the output file name which in our case is rpb. | | .-u argument is followed by the starting PROM address which for our case | is 0. |___ N.B. if you use 0 for the starting PROM address make sure you use an offset in the sload command. (to be explained later.) the other option is to specify an offset in the make prom command and have a zero offset in the sload command. The resultant file rpb.exo file is now ready to be downloaded to the RPB. 12. Turn on the power switch for the board. On your terminal, login to edson (from here on must be done from the station physically connected to the RPB.) In order to start talking with the board, you must initiate serial connection by using the UNIX tip command. From the shell prompt, type; shellprompt> tip gizmo Connection between shell and the board has been made now. If you hit the return key twice, you will see that your shell prompt will read: Gizmo2> If you do not get the Gizmo2 prompt, try to hit the return key again or by pressing the switch marked as RESET on the board. (top left hand corner) Any time if you wish to exit the monitor, type ~. For example: Gizmo2> ~. will help you exit from the monitor and get you back to the shellprompt. 13. First, you need to load the bit stream into RAM. Make sure that your transparent mode shell is in the same directory as FPGA data. Now, at the Gizmo2 prompt type Gizmo2> tm "tm" is the transparent mode command which places the user into transparent mode by establishing a software connection between the HOST and the TERMINAL. Moreover, this mode preempts normal communication between the TERMINAL and the debugger. In this mode, all keyboard input is relayed directly to HOST. HOST responses in turn are returned to the screen. (If you wish to go back to the monitor environment, use CTRL-a) After typing tm at Gizmo2 prompt, hit the return key twice and you will get the UNIX login prompt. Use your own login I.D. as well as your own password as follows: login: AAAA [ use your own login I.D] Password: [ use your own Password ] After logging in, change directory into your working directory and then change the directory to the Xilinx directory, containing the rpb.exo file. In our case: shellprompt> cd ~/vhdl/Xilinx Once you are in the desired directory, type CTRL-a at the shell prompt and, that will make you return to the monitor prompt. shellprompt> CTRL-a Afterwards you should be back in the monitor program and see the Gizmo2 prompt. Now, in order to download the FPGA data to the RAM, type the following command: Gizmo2> lo 40000 ;sload rpb.exo 40000 in the above command is used for defining the offset i.e. the FPGA data will be stored at address 40000. The reason for defining the offset here is that, while executing MakeProm command, we did not set any offsets. (refer to the note following the -u argument of the makeprom command for further details) the "lo" command is basically used for downloading S-Records from the host system. If an offset is present on the command line then, the target address is the offset added to the address determined by the S-Record. the "sload" command controls the handshaking with the monitor and will transfer the data in rpb.exo to the board and then check for errors while transmitting. During the transfer of data, you will see the following messages : offset==40000 ................................................................. S-Record load successful To program the FPGAs, we first we load the information from RAM to FPGA1, when the first FPGA is programmed, it passes the rest of the programming information to the second FPGA. All this is controlled by the microprocessor because the programming information is contained in a single block of memory. The following command is used to program the FPGAs: Gizmo2> lf 40000 the following prompt will be returned to the monitor: Okay to read FPGA data from RAM? (y/n) Type no other key but y and this will allow the lf command to download the data from memory location 40000 to the FPGAs. Any other key typed will abort the programming of FPGAs. You will observe the following messages: Initializing FPGAs ..... Number of bytes = ADF2 ...................................................... The programming of the FPGA is now complete. a binary counting pattern will be observed, with a couple of the low order bits, flashing very rapidly, or being on dim, but constant. (this is really just very rapid flashing) remember that the input is a 16 MHz clock. In the case of a general design, inputs would come from switches or from the MC68306 in which case a test program could be loaded into the RPB just the way the actual design was. WARNINGS AND ENVIRONMENT INFORMATION ------------------------------------ 1. The biggest problem that we faced was access to all the setup files and libraries. The part of this report assumes you are working on one of the workstations in cab 449. ensure that the following two lines appear in your .cshrc file: source /usr/local/rcfiles/Cshrc alias sload /CMC/RPB/binaries/sload/sload and ensure that this file is sourced. (i.e. type ) ensure that there is a file called .synopsys_dc.setup in your home directory. This file allows you to control the behaviour of fpga_analyzer upon startup. If you want to find out all about the possibilities of this file, study the file: /CMC/tools/synopsys.1997.01/admin/setup/.synopsys_dc.setup this file seems to give all options possible, but is nearly 1400 lines long, and is much more detailed than necessary. We used only the following file: company = "Electrical Engineering 552" ; designer = "Shazia Mardhani and Ray Still"; /* LIBRARY SETUP */ search_path = search_path + /rapid/part3/synopsys/xilinx/syn link_library = {"*" xprim_4010-6.db xprim_4000-6.db xgen_4000.db \ xio_4000-6.db xfpga_4000-6.db} target_library = {xprim_4010-6.db xprim_4000-6.db xgen_4000.db \ xio_4000-6.db xfpga_4000-6.db} symbol_library = xc4000.sdb which sets all necessary options. 2. The program fpga_analyzer is a part of the synopsys synthesis tools. Synopsys has all of there reference manuals on line. They are easily accessible through typing at the command line or selecting Help => On-Line Documentation... from the top menu bar. expect (i.e. ignore) "Warning: Unable to locate default Iview file" (this error can be corrected by copying /CMC/tools/synopsys/worldview/Iview into your home directory, but unless you really don't like to see error messages or you plan on using Iview lots and want to customize it, I don't think it's worth using the disk space to copy this file.) This opens two new windows, labeled Synopsys Online Documentation 1997.01 [short window] and Synopsys Online Documentation 1997.01 - Welcome to Synopsys Online Documentation:Synopsys Online Documentation [tall window] these two windows can give you access to literally thousands of pages of manuals, but the set that comes up first is the manual on using the manual. To get to the fpga_analyzer manuals, select File => Open Collection... from the top menu bar in the tall window. This brings up a small window labeled Open Collection. scroll down with the scroll bar until you can see Synopsys Synthesis Tools 1997.01 selecting this option gives another small window labeled Synopsys Synthesis Tools 1997.01 select one part of Design Analyzer Reference. (fpga_analyzer is just Design Analyzer with certain options preset.) when you select one of these, it is brought up in the tall window. the toolbar at the top and scroll bar along the side allows you to page through. (you can keep turning the page past the end of the section you selected.) (you can chose the table of contents any of four chapters, or the index.) At various places, you will find a blue "star" (checkerboard, whatever) This indicates hypertext. single click on this to go to wherever it points. To get back, click on "View" on the top menu bar, and select "Back" a word surrounded by a blue box is also hypertext, and is treated as above. Just because text is coloured, doesn't mean it is hypertext. following is a brief summary of the design analyzer manual: Design Analyzer is the graphical interface to the Synopsys family of synthesis tools: DC Expert, DC Professional, ECL Compiler, FPGA Compiler, Test Compiler, Test Compiler Plus, HDL Compiler for Verilog, and VHDL Compiler. The Synopsys VHDL System Simulator has its own graphical interface. Design Analyzer uses a mouse and pointer to select objects and commands. There is also a command-line interface, called dc_shell, in which you enter UNIX-style commands, arguments, and options. The command-line interface is described in the Design Compiler Family Reference Manual. To understand the Design Analyzer's graphic interface, you need to understand these concepts The above probably violates copyright law, but it is the first page of chapter 1 of the design analyzer reference manual. Chapter 1 is an overview of the capabilities of design analyzer chapter 2 contains an extensive list of all variables, and menu commands, and Graphical user interface instructions and also a description of the various reports available. chapter 3 goes into further depth on menus and Dialog Boxes. chapter 4 describes each Design Analyzer menu, submenu, and dialog box in alphabetical order according to the following menu bar items: Analysis Menu Attributes Menu Edit Menu File Menu Setup Menu Tools Menu View Menu Help Menu and includes equivalent commands, in most cases. Roughly 12 pages of hyper text index follows selecting Help => Commands... from the top menu bar in fpga_analyzer also gives help, but in this case you type in a command or error message, and fpga_analyzer tells you everything it know's about what you typed. (sometimes that's nothing.) 3. here are a lot of files and information generated by this whole process. many of the files are not human readable. There are some notable exceptions. The *.out files contain among other things preliminary utilization reports. The *.prp files contain a report for the user in quite readable form, which includes: Errors, Warnings, Clock Signals Report, Timing Specification Summary, and Logic Trimming. The *.rpt files contain another readable report including: Warnings, Device Utilization, Implementation Options, Performance Summary, Chip Pinout Description, Routing Summary, and Information in Other Reports. Other files that may or may not be present, containing reports are *.mrg, *.prx, *.blx, *.tsi (where *.blx indicates, for example, any file with blx as the extension.) (All *.log files are semi-readable and may be of interest or use.) CAUTION: fpga_analyzer accepts only a subset of VHDL. I.E. JUST BECAUSE YOUR VHDL COMPILES FOR MENTOR GRAPHICS, DOESN'T MEAN THE PROBLEM ISN'T IN YOUR CODE. for example, If you try to use if(clk'event and clock = '1' and enable = '1') then .. which is perfectly valid VHDL code. You get the error VHDL-2251 (error). when you check this error from fpga_analyzer menu Help => Commands... you get: Command Reference N. Messages messages NAME VHDL-2251 (error) Enabling expression not permitted outside wait statements %s DESCRIPTION This error occurs with statements of the form: if(clk'event and clock = '1' and enable = '1') then .. Such expressions are only permitted in: wait until clk'event and clock = '1' and enable = '1' ... at present WHAT NEXT Modify the if statement with the enabling condition to conform to suggested style. v1997.01 Synopsys Inc. 1988-1997. All rights reserved. n-1 -------- APPENDIX **************************************** counter.vhd **************************************** -- 30 bit synchronous counter -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count30 is port(Enable, clr, Clock : in std_logic; Q : out std_logic_vector(29 downto 0)); end count30; architecture behaviour of count30 is begin counter: process variable count :std_logic_vector(29 downto 0); begin wait until ( Clock'event and clock = '1' ); if clr = '1' then count := "000000000000000000000000000000"; elsif (Enable = '1') then count:= count + '1'; end if; Q <= count; end process counter; end behaviour; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity simple_counter is port(Clock: in std_logic; num: out std_logic_vector(29 downto 0)); end simple_counter; architecture instance of simple_counter is component count30 port (Enable, clr, Clock : in std_logic; Q : out std_logic_vector(29 downto 0)); end component; signal temp1,temp0: std_logic; begin temp1 <= '1'; temp0 <= '0'; count: count30 port map ( Enable => temp1, clr => temp0, Clock => clock, Q => num); end instance; -- code copied from ee 552 class notes sept 97 from Dr. Duncan Elliott -- modified by Dr. Duncan Elliott and Ray Still and shazia Mardhani ********************************** eg.script ********************************** analyze -format vhdl -lib WORK {"/lv1/ugrad/still/vhdl/counter.vhd"} elaborate simple_counter -arch "instance" -lib WORK -update create_schematic -size infinite -symbol_view create_schematic -size infinite -hier_view set_port_is_pad "Clock" remove_attribute find(port, "Clock") port_is_pad set_port_is_pad "num[6]" set_port_is_pad "num[5]" set_port_is_pad "num[4]" set_port_is_pad "num[3]" set_port_is_pad "num[2]" set_port_is_pad "num[1]" set_port_is_pad "num[0]" ************************************ ioplace1.script ************************************ /* Add in pin constaints here */ /* replace the description contained in the {} where appropriate */ set_attribute {"Clock"} "pad_location" -type string "U1" set_attribute {"num[18]"} "pad_location" -type string "C2" set_attribute {"num[19]"} "pad_location" -type string "A7" set_attribute {"num[20]"} "pad_location" -type string "A4" set_attribute {"num[21]"} "pad_location" -type string "A5" set_attribute {"num[22]"} "pad_location" -type string "A6" set_attribute {"num[23]"} "pad_location" -type string "A8" set_attribute {"num[24]"} "pad_location" -type string "A9" set_attribute {"num[25]"} "pad_location" -type string "A10" set_attribute {"num[26]"} "pad_location" -type string "A11" set_attribute {"num[27]"} "pad_location" -type string "A13" set_attribute {"num[28]"} "pad_location" -type string "A14" set_attribute {"num[29]"} "pad_location" -type string "A12" /*this is clock version. Clock pin was changed from V5 to U1*/ ************************************ fpga2.vhd ************************************ -- -- This is a connection component for the -- RPB and connects fpga1 to the LEDs -- CMC 96 -- Altered by Ray Still and Shazia Mardhani 1997 -- U of A Library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity fpga2 is port (num: in STD_LOGIC_VECTOR (11 downto 0); LED0 : out std_logic; LED6, LED9, LED12, LED13: out STD_LOGIC; LED1, LED2, LED3: out STD_LOGIC; LED4, LED5, LED7, LED8, LED10, LED11: out STD_LOGIC); end fpga2; architecture CONNECTION of fpga2 is begin LED0 <= num(0); LED1 <= num(1); LED2 <= num(2); LED3 <= num(3); LED4 <= num(4); LED5 <= num(5); LED6 <= num(6); LED7 <= num(7); LED8 <= num(8); LED9 <= num(9); LED10 <= num(10); LED11 <= num(11); LED12 <= '0'; LED13 <= '0'; end CONNECTION; ************************************ fpga2.script ************************************ read -format vhdl /lv1/ugrad/still/vhdl/fpga2.vhd /*this might be the wrong path*/ set_port_is_pad "*" insert_pads /* Add in pin constaints here */ set_attribute {LED0} "pad_location" -type string "L2" set_attribute {LED1} "pad_location" -type string "L3" set_attribute {LED2} "pad_location" -type string "M1" set_attribute {LED3} "pad_location" -type string "M2" set_attribute {LED4} "pad_location" -type string "N3" set_attribute {LED5} "pad_location" -type string "P1" set_attribute {LED6} "pad_location" -type string "P2" set_attribute {LED7} "pad_location" -type string "T2" set_attribute {LED8} "pad_location" -type string "C2" set_attribute {LED9} "pad_location" -type string "C4" set_attribute {LED10} "pad_location" -type string "E1" set_attribute {LED11} "pad_location" -type string "V3" set_attribute {LED12} "pad_location" -type string "E16" set_attribute {LED13} "pad_location" -type string "E17" set_attribute {"num[0]"} "pad_location" -type string "V2" set_attribute {"num[1]"} "pad_location" -type string "V7" set_attribute {"num[2]"} "pad_location" -type string "V4" set_attribute {"num[3]"} "pad_location" -type string "V5" set_attribute {"num[4]"} "pad_location" -type string "V6" set_attribute {"num[5]"} "pad_location" -type string "V8" set_attribute {"num[6]"} "pad_location" -type string "V9" set_attribute {"num[7]"} "pad_location" -type string "V10" set_attribute {"num[8]"} "pad_location" -type string "V11" set_attribute {"num[9]"} "pad_location" -type string "V13" set_attribute {"num[10]"} "pad_location" -type string "V14" set_attribute {"num[11]"} "pad_location" -type string "V12" compile replace_fpga set_attribute fpga2 "part" -type string "4010pg191-6" set_attribute find(design,"*") "xnfout_use_blknames" -type boolean FALSE write -format xnf -hierarchy -output Xilinx/fpga2.sxnf