• Combing VHDL & Schematic Capture Components
• Mapping VHDL library:
• Converting netlist file to VHDL for back annotation
• Mapping Clock Signal
• Unexpected signal in simulation after back-annotation
• Unsigned Library in ACTMAP
• Debug the design in simulation

Both VHDL and Schematic Capture have their own benefits when it come to digital designs. VHDL allows for flexible higher level description of a design and save a great deal of time when it comes to synthesizing certain predefined components such as ACTGEN’s counters and arithmetic units. Schematic Capture on the other hand allows the designer to get down to the gate level and manipulate logic to save space and improve efficiency. Something the computers aren’t as good as the human. Even through, both techniques are quite good, it is sometimes quite useful to design some components in one method and other components with another method. The following method is used to compile components from VHDL and Schematic Capture into one large system.

STEP 1: Develop the Schematic Capture Component (If you wish, you may start from step two). Keep in mind the delay factor when you finally combine the components.

STEP 2: When finished with the Schematic Capture component, use the following command to convert it to edn netlist file:

mgc2vhdl fam:act1 <design name>

Once finished, move the edn file from within the <design name> directory to your project directory or a common directory where you are going to compile all your components to edn netlist files.

STEP 3: When finished with the VHDL component, compiled it with ACTMAP. You may optimize it as you see fit (area, speed or no optimization). This will create a edn or edo netlist file in you directory. Warning: the name you choose for the edn or edo file should be in the name of your component entity.

STEP 4: Writing a top level VHDL monitor. Do not use any "use" statement for your components you have designed. Otherwise declare the same as before you would declare a component in VHDL. : e.g.

Warning: Make sure that the component name you declare is the same as the edn file name:

For example: ee552proj.edn

STEP 5: Compile the top level monitor in ACTMAP. Warning: Remember to compile your top level code in Chip Mode. If you see instantiating black boxes for your component, don’t be afraid. Actually this is good thing, it means you are almost there. All those warning messages just means that the ACTMAP at this point don’t know what these components you declared to be is and it is just setting up the connections just in case you do have something to fill in.

STEP 6: When you have finished with compiling and optimizing the top level VHDL monitor. Go to the netlist translate menu, you access this by clicking the translate button from your current actmap menu or from the main ACTMAP menu under File. Choose the top level edn or edo netlist file as source and indicate the output format as Designer and hit the translate button. Also remember to set the Merge Block option. If successful, you will see this message:

The following modules have been compiled :

<component name 1>

<component name 2>

.

.

.

When all is finished, your full design will be translated into a <design name>.opt file. Remember, this file is in ADL format.

STEP 7: Be patient, I know this seems like a lot of steps. We are almost done. Now open up designer. After you have set your regular chip parameters, go to File and choose Import Netlist file. Select your opt file and set the input format as ADL. Warning: Must set the Naming Style to VHDL, otherwise you will have bad time trying back annotate. By choosing the naming style as VHDL, it will map all the Schematic Capture character in you Schematic Capture component code into VHDL accepted variable names. You may now hit the OK button and start compiling the design.

STEP 8: Once you have compiled the design successfully (sorry, can’t help you if your design doesn’t work). You may go to the File Menu and click export, choose the Netlist as output format and a name. This will create an edn file in you directory you can use to do simulation without delay. See the compile edn file for back annotation section to see how this is done. If you have done the extraction of the delay file, you may simulate with delay.

Note: I know this is a lot and you are eager to start on the project. There is a intermittent problem I experienced with the designer compiling the opt file. If you received a error message in designer when compile stating: comp 032 error. The following trick has helped me a few times. Open the edn file you created with the top level VDHL monitor file, and find the port listing indicate for your component in Schematic Capture. Copy and paste that port listing to the same port listing in the edn file you created for the Schematic Capture component. Do not attempt this if you have modified I/Os in you design.

This method is slightly different than linking the file from other sources.

qhmap act1 $ALSDIR/lib/vtl/95/qhdl/act1

STEP 1: Make sure you have correctly mapped the ACT1 library. You can do this by opening the quickhdl .ini file with any editor and see if the third line contain a line indicating

Library]

If the quickhdl file is not mapped properly, you may wish to see how to map the VHDL library by reading the section on Mapping VHDL library.

STEP 2: Use the following command to convert an edn file to VHDL structure code contain act1 gates:

edn2vhdl fam:act1 <design name>

STEP 3: Now to compile the VHDL code, if you don’t have work directory, you may create on using the following command.

qhlib work

Once you have a work directory, use this command to compile the code:

qvhcom <design name>.vhd

STEP 4: You may open qhsim, either from command line by typing :

qhsim for simulation with no delay

qhsim –sdftyp <design name>.sdf for simulation with typical delay

Note : when choosing the component for simulation, remember to choose the structure architecture created from the edn netlist file. General it will be using the name def_arch.

Mapping clock signal is useful when ACTMAP doesn’t detect you clock signal, or when you clock signal is gated, at which case ACTMAP won’t use you that signal as in conjunction with the clock buffer.

When compiling you VHDL code in ACTMAP, if you notice there is not clock network define you may going to the option menu in the netlist optimize menu and click Define I/O. This will pop up a little text box where you can indicate the signal name you wish to use for the clock. When you optimize the design, the program will find that I/O and connect it to a clock buff. Warning: you must have to have chip mode option in order to use this function in the menu.

Note: This only seems to work within the optimizer, although this function is also defined in the VHDL compiler in ACTMAP. Using the above procedure doesn’t seen to create the clock properly.

It is very useful to be able to declare an ACTEL component in your VHDL code. Perhaps a simple XOR gate between the interconnections of your design. The way to do this is to declare act1 component. Do not use the use command, simply declare the component the way it is declared in the comp.vhd file. You may locate this file under

/opt1/actel/lib/vtl/95/qhdl/act1 directory. When compile the code in ACTMAP, you will see the warning "instantiating black box". Do not be concerned with this, if you have the correct library mapped (see Mapping VHDL library). It should has place the correct component in the place of the black box when you compile your design in designer. You may then export the edn netlist file for back annotation (see Converting netlist file to VHDL for back annotation).

Even the VHDL code has passed the functional simulation, it may still fail when it is being tested after the back-annotation. It is usually caused by the glitch in the state machine signals. Since all the logic become structural description after back-annotation, different signals can have different time delay for them to change. This may cause glitch

in a signal. When there is glitch in the state machine signals, this may cause change of other signal even it is not related to the expected state. To solve this problem, all signal need to be describe explicitly in each state. This can change all the output signal to its expected value but causing a glitch for them

Even the VHDL code has passed the functional simulation, it may still fail when it is being tested after the back-annotation. It is usually caused by the glitch in the state machine signals. Since all the logic become structural description after back-annotation, different signals can have different time delay for them to change. This may cause glitch

in a signal. When there is glitch in the state machine signals, this may cause change of other signal even it is not related to the expected state. You may use the following method in removing these problems:

• Define all signals at the start of each state.
• Make sure only one signal can change each state.
• Design all components as synchronous components

The library STD_LOGIC_UNSIGNED is commonly used in VHDL file. This library is necessary when a VDHL file with some unsigned standard logic is compile in design architect. However, this library may cause problem when this file is compile in actmap. To solve this problem, the library is comment out in the file whenever it is compile in ACTMAP.

One way to verified the design in simulation is to check the state of the system. Even after the back-annotation of the system, the state signal can be examined from the structure of your back annotation in the qhsim. The compiler of ACTMAP will convert all the state of the VHDL code into a binary form which is in the order your describe in the state type description. VHDL code can be more easily to debug when there is state signals in the simulation. Instead of using types in defining state, try using actual signal such as "00001" represent a state.