Student Contributed Documentation

					by

          		Dale Pethick 	and 	Ronald Gil


Getting Started With Your Project

	Starting out can be one of the most difficult things to do when it 
comes to deciding what you want to do for a project. When my partner and I 
first started, we wanted a project that would not be to overly ambitious, but 
at the same time be to easy  to implement.  So, how do you choose your project?
Well, that is up to you, there are numerous ideas available at Dr. Duncan 
Elliott's home page, but one thing you should keep in mind, is keep the design 
small. We can't stress this enough! For one, if you start small you can always 
add more to your design later. You'll base this on the number of modules your 
chip is taking up. If your close to the maximum, its quite obvious that your 
not going to waste time adding more. Two, its a lot easier adding to your
design then trying to figure what to slice from your design. This causes many 
painstaking hours and headaches beyond belief. 

	Another thing you should keep in mind when doing this project is time 
management.  Most of you will probably be taking five other courses along side 
of this one. This project is going to eat up a lot of your time, so get started 
early! Decide on a project and get going. Strive to get about 2 weeks 
ahead of your deadlines.  This may seem a little drastic, but by the time you 
get to your simulation and back-annotation, you'll probably be just on 
schedule.  

	One last point, make sure you have a good understanding of VHDL.  This 
will help a lot.  If your in the process of learning VHDL or not the expert, 
as most of us are, you'll want to find some good reference materials.  Some 
can be found on the web, but there are some books that my partner and I 
recommend looking at. VHDL Made Easy by David Pellerin and Douglas Taylor, and 
VHDL for Programmable Logic by Kevin Skahill.

Okay, now down to business.....

Over the course of this project, my partner and I have encountered many 
pitfalls and problems in our project.  Some of the problems we overcame while 
others forced us to modify our actual design.  The following is compilation of 
what we learned about the design tools, which we divided into two sections,  
VHDL synthesis and  back annotation and simulation on the Actgen  Design Tools.

Section 1:	VHDL Synthesis

During the course of this project we had to choose between a schematic 
synthesis or behavioral synthesis .  Our decision to go with behavioral
synthesis was based on the following:

	*more intuitive reasoning in design (especially with combinational 
	 logic)
	*less demand to know the intricacies of Actel schematic layout since 
	 the designer is shielded from the FPGA by the synthesis tools.

First thing to do is break your code down as much as possible.  Make your 
design as modular as possible.  Break it into components and sub-components 
yet if you can, thereby reducing the amount of possible debugging later (and 
there will be lots).  This saves you a lot headaches, and makes sense.  Don't 
bite of more than you can chew! Do a component, get it working, then move on. 
Don't try to juggle it all at once.

Once you have all your VHDL code written, it would probably be a good idea to 
back-up these files.  This is a good idea any time, due to fact that a file 
could get overwritten, deleted or in that odd case that something doe goes 
wrong. ;)  My partner and I have had many a time when a file has been destroyed 
due to Mentor Graphics crashing.  

When it comes time to compile your code, make sure you set up a default 
directory first, such as "work". This can be done by going to the "Compile" 
menu and selecting "set options" (I think that's what it is). A selection table 
will pop up where you can designate the directory in which save your compiled 
data.  Just make sure you know where this directory is, because your going to 
need the files for your simulation. If you forget to do a directory, design 
architect will create a sub-directory in your current one, as well as the 
file _info and _lock.  You can do your simulating this way, but you won't be 
able to edit your .vhd file, due to _lock. Just remove the sub-directory and 
the two files, and create the "work" directory.

When doing your project you'll come across numerous problems, some of which 
your peers will encounter as well. 

If-then-else statements.  This is a biggy.  When writing your code, try to 
stay away from the else statements. Use "elsif" instead. This will save you a 
lot of modules later on.  This is manly due to the fact to the fact that 
"else" takes into effect all of the unmentioned logic. (special thanks to Mike 
Daskalopoulos for the tip)

An example of this is:
	if  DA = '1' then
		Q <= "00000000";		(Avoid)
	else 
		Q <=D;
	end if;
	if  DA = '1' then
		Q <= "00000000";		(Correct)
	elsif  DA /= '1' then 
		Q <=D;
	end if;

	
Section2:	Back Annotation and Simulation on the Actgen
		
Now that you have all your components, compiled and simulated,  you can move
onto back-annotation and simulation on the Actgen.  However, first you have to
do a minor change to your VHDL code. If you're compiling using Actmap,
you'll want to use the library: 

           use ieee.std_logic_arith.all; 

Actmap will substitute std_logic_arith with its asyl library equivalent when 
you compile.  For some reason this works, but I'm not to sure why.

Once you've made that change, load up Actmap.  This can be done by typing

		actmapw &

at the terminal.  This will open up Actmap.  Now follow the procedures from 
your lab on back-annotation.  You'll want produce and .edo file that you
can use in the designer. 

As you are going through the compiling, check to see the number of modules your 
components or top level is taking up. Remember, you can only have 295 modules
for the A1010 series, and 547 modules for the A1020 series. (These are for the
ACT1 family).  If you've exceeded that amount, your going to edit your VHDL
code or slice something from your design.  This is why you start small.

Now that you've finished Actmap, its time to put those .edo files to good use.  
Open up designer in your terminal by typing

		designer &

at the terminal. Run through the compiler and other functions, and then run 
"Fuse".  This will produce the .afm file you need to burn your chip. However, 
you better run a simulation before you burn your chip.  Just because you 
produced a working result in QHSIM before does not mean your design works. The 
"Extract" button will produce a file that you can use to simulate your actual 
design.

From here you can load up QHSIM again and test your circuit to make sure it 
works. If all goes well, give your .adm file to your professor, so s/he can 
burn your chip.