-- this three in one processor is the latest craze.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity processor is
	port(
				reset, 
				clock,
				sample_ready,
				noise_gate,
				peak_ready
				
					 	: in std_logic;

				tune_bus  : in  std_logic_vector(15 downto 0);
				otune_bus : out std_logic_vector(15 downto 0);

				process_complete
					
						: out std_logic
				
 			);
end processor;

										

architecture behavioural of processor is

type state_type is (read_sample,read_peak,end_process);

signal process_state, next_process_state : state_type;


		signal 	sample	: std_logic_vector(15 downto 0);
		signal	peak 	 	: std_logic_vector(15 downto 0);
		signal  esample : std_logic_vector(15 downto 0);
		signal	epeak	 	: std_logic_vector(15 downto 0);
		signal  flag		: std_logic;
															
	
	

begin


	rock : process(noise_gate,tune_bus,process_state,sample_ready,peak_ready,reset)

	begin

		if reset = '1' then
			next_process_state <= read_sample;
			process_complete   <= '0';
			flag <= '0';
		end if;

		case process_state is
	
				when read_sample =>

						if sample_ready = '1' then
							sample				 				<= tune_bus;
							next_process_state 		<= read_peak; 
						else
							next_process_state 		<= read_sample;
						end if;	
						process_complete <= '0';

				when read_peak =>

						if peak_ready = '1' then
							peak 	<= tune_bus;
							if sample(15) = '0' then
								esample <= sample(13 downto 0) & "00";
								epeak   <= "00" & peak(15 downto 2);
								flag <= '0';
							else
								sample <= -sample;
								flag <= '1';
								esample <= sample(13 downto 0) & "00";
								epeak   <= "00" & peak(15 downto 2);
							end if;
							next_process_state 		<= end_process;

						else
							next_process_state <= read_peak;
						end if;


				when end_process =>

            if noise_gate = '1' then
							otune_bus <= "0000000000000000";

						elsif sample >= epeak then
							if flag = '1' then
								otune_bus <= -peak;
							else
								otune_bus <= peak;
							end if;
						else
							if flag = '1' then
								otune_bus <= esample;
							else
								otune_bus <=  esample;
							end if;
						end if;
			
						process_complete <= '1';
						next_process_state <= read_sample;
				
		end case;

	end process rock;

	state_register : process(clock,reset,next_process_state)

	begin
		
		if reset = '1' then
			process_state <= read_sample;
		elsif clock = '1' and clock'event then
			process_state <= next_process_state;
		end if;
	end process state_register;	

end behavioural;