read -format vhdl /lv1/ugrad/still/vhdl/fpga2.vhd /*this might be the wrong path*/
set_port_is_pad "*"
insert_pads
/* Add in pin constaints here  */
   set_attribute {LED0} "pad_location" -type string "L2" 
   set_attribute {LED1} "pad_location" -type string "L3"
   set_attribute {LED2} "pad_location" -type string "M1" 
   set_attribute {LED3} "pad_location" -type string "M2" 
   set_attribute {LED4} "pad_location" -type string "N3" 
   set_attribute {LED5} "pad_location" -type string "P1"
   set_attribute {LED6} "pad_location" -type string "P2"
   set_attribute {LED7} "pad_location" -type string "T2"
   set_attribute {LED8} "pad_location" -type string "C2"
   set_attribute {LED9} "pad_location" -type string "C4" 
   set_attribute {LED10} "pad_location" -type string "E1"
   set_attribute {LED11} "pad_location" -type string "V3" 
   set_attribute {LED12} "pad_location" -type string "E16"
   set_attribute {LED13} "pad_location" -type string "E17"
   set_attribute {"num[0]"} "pad_location" -type string "V2"  
   set_attribute {"num[1]"} "pad_location" -type string "V7"   
   set_attribute {"num[2]"} "pad_location" -type string "V4"   
   set_attribute {"num[3]"} "pad_location" -type string "V5" 
   set_attribute {"num[4]"} "pad_location" -type string "V6"
   set_attribute {"num[5]"} "pad_location" -type string "V8" 
   set_attribute {"num[6]"} "pad_location" -type string "V9" 
   set_attribute {"num[7]"} "pad_location" -type string "V10"  
   set_attribute {"num[8]"} "pad_location" -type string "V11"   
   set_attribute {"num[9]"} "pad_location" -type string "V13"   
   set_attribute {"num[10]"} "pad_location" -type string "V14" 
   set_attribute {"num[11]"} "pad_location" -type string "V12"  
compile
replace_fpga
set_attribute fpga2 "part" -type string "4010pg191-6"
set_attribute find(design,"*") "xnfout_use_blknames" -type boolean  FALSE
 
write -format xnf -hierarchy -output Xilinx/fpga2.sxnf