Student Contributed Documentation - Bug Fixes and Work-Arounds

Bugs Fixes and Work Arounds

Througout our project, we have faced many problems and would like to share how to fix/work around these problems.

Size of the project

Don't be too ambitious. The project you are designing can be as big as you want. But keep in mind that you need to implement it into Actel/Xilinx chip. The suggestion is to use one chip only. So, with the Actel/Xilinx chip available now, you only allow to use as many as 547 modules. This may sound a lot but in reality, 6 to 7 entities will used up that amount. So, several features of the project may need to add or remove. But the most important thing is to have something(basic stuff) to demostrate.
Time Scheduling

Start to do your project as soon as possible. Also, work ahead if possible as the simulation part will take up a lot of time. The VHDL coding that works perfectly when simulate may not be able to run extracted Actel FPGA timing simulation as Actel doesn't support some part of the VHDL coding. (details below) plan ahead so that you have enough time to finish the project
VHDL Coding

For VHDL, it doesn't support any global variables among processes. As well, a signal cannot be used as output in two processes. For example,

--This does not work as enable is used as output in two processes
process(up)
begin
if up = '1' then
enable <= '1';
end if;
end process;

process(down)
begin
if down = '1' then
enable <= '0';
end if;
end process;

-- Try this
process(up, down)
begin
if up = '1' then
enable <= '1';
elsif down = '1' then
enable <= '0';
end if;
end process;
VHDL Coding -> Actmap

There are several VHDL codes that are incompatible when converting into Actel for back annotation. Watch out!
- Library
  If you use arithmetric in your project, you should change the library when you compile the code in Actel Actmap. You are not allowed to use the library ieee.std_logic_arith.all.
  
  library ieee;
  use ieee.std_logic_1164.all
  --use ieee.std_logic_arith.all;
  
  libary asyl;
  use asyl.arith.all;
- Wait/Delay statement
  Do not use any wait/delay in VHDL code. Although you can use wait/delay in your VHDL code and works fine in simulation, Actmap does not support these statements. This criteria is crucial when you want to increment the time. Instead, you should try to use a separate counter to do the timer. You can refer to our digital clock for example.
- If statement
  Avoid nested if statement as it will greatly increase the complexity and the number of modules needed. As well, if possible, try to use case statement indeed.
  
  -- Avoid using if statement if possible
  if state = "00" then
  statement ......
  elsif state = "01" then
  statement ......
  elsif state = "10" then
  statement ......
  -- Use case statement indeed
  signal state :std_logic_vector(1 downto 0);
  ......
  ......
  case state is
  
  when "00"=> statement ......;
  when "01"=> statement ......;
  when "10"=> statement ......;
  when others => NULL;
  
  end case;
- Event
  For Actel chip, it is not allowed to look at multiple variables' event in the same process. So, split the process into two.
  
  -- This won't work
  process(clock, up)
  begin
  if rising_edge(clock) and rising_edge(up) then
  statement ......
  end if;
  end process;
  
  -- Try using two processes
  process(clock)
  begin
  if rising_edge(clock) then
  statement .......
  end if;
  end process;
  
  process(up)
  begin
  if rising_edge(up) then
  statement .......
  end if;
  end process;
- Synchronous/Asychronous
  Avoid using asychronous condition and try to make everything synchronous, i.e. repsonse to rising edge/falling edge of the clock. Otherwise, some strange result may happen when you do back annotation.
  
  -- Avoid this asychronous statement
  process(up)
  begin
  if rising_edge(up) then
  statement .......
  end if;
  end process;
  
  -- Use this indeed
  process(clock, up)
  begin
  if rising_edge(clock) and up = '1' then
  statement .......
  end if;
  end process;
- Clock
  You would probably requires several clock frequencies for the project. Keep in mind that only 1 clock is allowed in the Actel chip. To have several clock frequencies, you can write a clock divider entity to provide different clock frequencies. However, you may have fan_out problem if you do that. Another way to solve this is to use external circuit, like 555 timer to change the frequency.
- Reset
  When you use case statement in Actmap, it requires to assign a initial state to the variable. For VHDL, the following statement
  type state_type is (start, normal, setting)
  state: state_type
  will initialize state to be start during simulation. However, it doesn't work in Actmap (at least for us). To solve this problem, you can set up a reset button that reset the state to the start state at the beginning.
  
  if reset = '1' then
  state <= start;
  end if;
  ......
- Hidden Character
  For some reason, after you actmapw your VHDL code, sometimes, there may be some hidden characters created inside your code (weird !!!) so that you won't able to compile it again. In this case, you can either manually re-type the whole entity (painful) or save a backup copy before and rename that copy to a new name and compile.

Author:

Cheong Wong

Norman Chan