TUTORIAL

COMPILE, SYNTHESIZE AND DOWNLOAD VHDL FILES INTO RPB IN UNIX COMMAND SHELL

Submitted as STUDENT CAD DOCUMENTATION by Chee Yoon Lee and Zixiong Wang for term project ‘Viterbi Decoder for Convolutional Coded Signals’.
Last updated : 3 DEC 1997

This documentation gives an alternative in using Design Architect Compiler, Synopsys Synthesis Tools and programming the Rapid Prototyping Board(RPB) at the UNIX command shell.

This documentation is especially useful if the design is intended to be remotely compiled, synthesized and to be remotely programmed into the Rapid Prototyping Board(RPB).

The steps are summarized as follows:

 

Step 1 - Compiling VHDL files using Design Architect

 Make sure the './work' directory is in your project directory. The file '_info' must be in the './work' directory.
 At your project directory:

This command will compile the VHDL file 'design_name'.

For example:

 Use the UNIX text editor, 'vi design_name.vhd' to fix the error found during compilation.

 

Step 2 - Simulation

 Note : This step requires that you are using a local UNIX workstation running windows.This step cannot be run remotely. Enter the QHSIM tool by entering the following command:

Make sure that the test file has been successfully compiled using qvhcom as shown in Step 1. In QHSIM, click on
the entity and architecture to be simulated and press 'Load'.

 

Step 3 - Synopsys DC Shell

Synopsys startup file, .synopsys_dc.setup must be modify to reflect the hardware configurations
and to ensure that the correct libraries are being used. For the Rapid Prototyping Board(RPB)
the .synopsys_dc.setup startup file is configured as follows:
 
The Synopsys startup file must be located in the user's root directory. The ‘./WORK’ directory
must be in the current project directory.
 
Enter the Synopsys DC Shell environment by entering the following Synopsys command on the UNIX
command line:
 
 
You will see the DC Shell prompt.
 
 
Behavioral Compiler (TM)
DC Professional (TM)
DC Expert (TM)
FPGA Compiler (TM)
VHDL Compiler (TM)
HDL Compiler (TM)
Library Compiler (TM)
Power Compiler (TM)
Test Compiler (TM)
Test Compiler Plus (TM)
CTV-Interface
DesignWare Developer (TM)
DesignTime (TM)
DesignPower (TM)
Version 1997.01 -- Dec 13, 1996
Copyright (c) 1988-1996 by Synopsys, Inc.
ALL RIGHTS RESERVED
 

Step 4 - Analyzing the Design

To interpret your design and verify that it is free of errors, enter the following Synopsys command for VHDL designs:
 
If the analyze command finds errors, you will need to make the necessary corrections to your source file and repeat the analyze command before continuing with synthesis.
 
For multiple level hierarchical designs, analyze all the low level as well as top level VHDL files for this step.
 

Step 5 - Elaborating the Design

 To derive a logical design, based on your VHDL description, enter the following Synopsis
command at the dc_shell:
 
where entity_name is the name of your top-level entity in your design.
 
For multiple level hierarchical designs, elaborate only the top-level entity.
 

Step 6 - Defining I/O Signals

Now you must define which signals are connected to the physical I/O pins of the FPGA.
 
Use the following command to identify all the ports for which the synthesizer needs to infer
an I/O buffer:
 
 
Do not use this command for any ports for which you instantiated I/O buffers cells from the library.
 
To automatically place I/O buffer cells on all top-level ports in the design, enter the following Synopsys commands:
 
 
You might want to eliminate the buffers from the clock input and the reset input. The Synopsys commands are as follows:
 
where clock and reset are your clock input and reset input.
For the ports that were specified by the set_port_is_pad, the following command infers
the appropriate I/O buffer cells into your design:
 
 
Note: If you want to control output slew rate, the DC Shell set_pad_type command must be invoked before the insert_pads command.
 
Step 7 - Specifying Attributes
 
Attributes are used to control the physical implementation of your design; all attributes are optional. For the RPB board, you need to set the attribute for the pin assignments for each physical port.
 
Use the following command to assign ports in your design to corresponding pins in the FPGA.
 
 
where "clock" is the system clock for your design and "U1" is the hardwired pin in the RPB to the 16MHz clock. "output_port" is the output_port for your design and "U14" is pin 39 of photoconnector A of FPGA1 in the RPB. Please refer to the RPB user manual for the pin number and the corresponding string. This command has to be done for all the input and output ports of your design. A script file might be useful here. To execute the script file:
 
 
where design.script is your script file. A sample of the script file is as follows:
 

Step 8 - Compiling the Design

When you compile your design, the Synopsys synthesizer uses the components in the specified Xilinx FPGA technology library to create an actual implementation of your design. The library used during compilation is defined by the DC Shell target_library variable, typically specified in your .synopsys_dc.setup file.
 
To synthesize an implementation of your design based on the specified Xilinx Series library, enter the following Synopsys command:
 
 
The mapping effort parameter is optional. However, it is recommended that you set it low to save compilation time because the synthesizer does not perform any speed or area optimization for FPGA designs; optimization is performed by other design fitter tools.
 

Step 9 - Creating the Area Report

 
The FPGA compiler reports are with the Report FPGA command as follows:
 
 
The statistics reported by this command include the number of the following elements used in your design.
This command also reports the number of CLBs used for the design on the basis of the mapping performed by the FPGA compiler.
 
This command must be run after the design has been compiled because the Compile command maps the logic into CLBs and IOBs. Run this command before replacing the CLB and IOBs with gates, that is before running the Replace FPGA command which is the next step.
 

Step 10 - Replace FPGA

 After compiling, a design contains CLB and IOB elements that the FPGA Compiler uses to determine the best implementation of a design for a given set of constraints. Before creating the SXNF file, you must convert these CLBs and IOBs into gates that can be recognized by the XACT Development System. The mapping information is passed to the SXNF file using the FMAP, HMAP and BLKNM parameters(ran automatically by XMAKE), so PPR can map the design.
 
Enter the following command at the command line at the top level of you design
 
 
Step 11 - Setting the Design Part Type
 
Type the following command at the command line to select a specific target part for the design. For the RPB, the target type is 4010pg191-6 device.
 
 

Step 12 – - Removing the Synopsys Mapping

By default, the FPGA Compiler XNF Writer contains information on how it should map the logic into the CLB and IOBs. The FPGA Compiler uses the FMAP and HMAP symbols to map Boolean logic into F and H generators, and the BLKNM attribute to group flip-flops and function generators into a CLB.
 Mapping information from the FPGA Compiler is usually efficient; therefore, the mapping is left on. Block names, however, can restrict placement and routing. For this reason, BLKNM attributes are removed.
 
To remove the setting of BLKNM attributes, enter the following at the shell:
 
Step 13 – - Saving the SXNF file
 
After replacing the design with gates, save the design to an SXNF file. The output file extension is .sxnf to distinguish this file from other XNF file. Enter the following command at the shell. (Make sure the top level of the design is selected)
 
 

Step 14 – - Translating into BIT files

 
To use the XACT Development System, the design must be translated to LCA and BIT files so that XACT tools can program the Xilinx 4000 device. This id done by invoking Xmake.
 
Quit the dc_shell by entering the following command:
 
 
At the UNIX shell, enter the following command:
 
 
Xmake will automatically translated X-BLOX modules into gates by running X-BLOX and maps, places and routes the design using PPR. Here, a BIT file called design.bit is created.
 
Step 15 – - Translating BIT files to Exormax(S-record) format file
 
To transmit hardware code to the RPB, the BIT file has to be translated to the Exormax(S-record) format file. On the shell prompt, enter the following command:
 
 
The command line arguments are as follows:
 
Here a file called design.exo is created in the current directory.
 
Step 16 – Downloading .exo file into RPB
 
Please refer to Step 12 of Ray Still and Shazia Mardhani’'s CAD tool documentation.