-------------------------------------
-- package for pll stuff
--
-- my_id : 	increment decrement circuit 
-- 			for adjusting the clock edge timing
-- my_counter : up down counter 
--				for determining commands to send to the i/d
-- my_divn : 	divide by N
-- 				for generating new clock

library ieee;
use ieee.std_logic_1164.all;

package pll_parts is


component my_id
	port( clock : in std_logic; 
		  increment, decrement : in std_logic;
		  slow_clock : out std_logic); 
end component my_id;

component my_counter
	generic ( width : positive := 8;
			  top_value : positive := 128);

    port( updown, clock : in std_logic; 
		  bout, cout : out std_logic); 
end component my_counter;

component my_divn
	generic ( width : positive := 8;
			  top_value : positive := 128);

    port( clock : in std_logic; 
		  cout : out std_logic;
		  reset : in std_logic); 
end component my_divn;

end package;