----------------------------------------------
-- PLL
-- this component uses the input pulses from the motor rotation sensor
-- to generate a synchronised clock for the display decoder
-- it is a fully digital Phase lock loop
-- the reference clock is taken from the onboard 25MHz oscillator

--INPUTS: signal from optical sensor on motor, reference clock
--OUTPUT : syncronised clock for display functions

library ieee;
use ieee.std_logic_1164.all;

--library my_pll;
use work.pll_parts.all;

entity phase_lock_loop is
	port (	ref : in std_logic;
			motor : in std_logic;
			new_clock : buffer std_logic;
			reset : in std_logic
		 );
end phase_lock_loop;

architecture sync of phase_lock_loop is

signal incr, decr, int, diff, always_on : std_logic;

begin
	--phase detector
	diff <= new_clock xor motor;	-- is high when the clocks are different

	-- up/down counter
	-- LPM counter doesnt have a borrow output?
	k_counter : component my_counter
				generic map ( width => 12, top_value => 2850) 
				-- too slow generic map ( width => 12, top_value => 2849) 
				port map (clock => ref, updown => diff, cout => incr, bout => decr);

	-- inc/dec
	-- this will divide the clock by two if no inc/dec requests are received
	-- if an inc request: then 2count is upped by 1, this moves the clock ahead a half cycle
	-- dec subtracts 1 from 2count. lags a half cycle.
	i_d : 	component MY_ID 
			port map (increment => incr, decrement => decr, clock => ref, slow_clock => int);

	-- divide by N
	div_N : component my_divN
				generic map (width => 13, top_value => 5700) 
				-- too slow generic map (width => 13, top_value => 5698) 
				-- too slow generic map (width => 13, top_value => 5699) 
				port map (clock => int,  cout => new_clock, reset => reset);
	 

end sync;