------------------------------------------------- 
-- Output Decoder
-- 
-- Written by:  B. Ryan Northcott (0252494)
-- Source:      
-- Date:        8 Feb 2001
-- Course:      EE 552
--
-- This code takes an input clock from a PLL and 
-- uses it to send the correct output to the 5
-- LEDs on the armature.
--
--------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library work;

entity outputdecoder is
    generic( Ni : positive := 20;  -- Number of input lines per channel
		     S : positive := 10;
		     E : positive := 30;
		     No : positive := 5;   -- Number of channels / outputs
			 Nc : positive := 5 ); -- Number of control lines
    port( in1  		: in std_logic_vector(Ni-1 downto 0);
          in2  		: in std_logic_vector(Ni-1 downto 0);
          in3  		: in std_logic_vector(Ni-1 downto 0);
		  in4  		: in std_logic_vector(Ni-1 downto 0);
		  in5  		: in std_logic_vector(Ni-1 downto 0);
		  PLL_Clock : in std_logic;
		  reset		: in std_logic; -- Active low
          LEDs 		: out std_logic_vector(No-1 downto 0) );
end outputdecoder;

-- structural implementation of the output decoder

architecture structural of outputdecoder is

component MuxN_1 is
	generic
	(
		N : positive := 20;	-- Number of input lines
		C : positive := 5	-- Number of control lines
	);
    port
	(
		Input   : in std_logic_vector( N-1 downto 0 );
		Sel     : in std_logic_vector( C-1 downto 0 );
		Output  : out std_logic
	);
end component;

component OutputCounter is
	generic
	(
		N : positive := 80;	-- Max Count
		S : positive := 10;	-- Start the Display
		E : positive := 30;	-- End the Display
		C : positive := 5;  -- Number of Mux Control Lines
		D : positive := 7   -- Number of bits in counter
	);
    port
	(
		PLL_Clock : in std_logic;
		reset	  :	in std_logic;
		MuxSel    : out std_logic_vector( C-1 downto 0 )
	);
end component;

signal iCtrl : std_logic_vector(Nc-1 downto 0);
signal iIn1, iIn2, iIn3 : std_logic_vector(Ni-1 downto 0);
signal iIn4, iIn5 : std_logic_vector(Ni-1 downto 0);
signal iLEDs : std_logic_vector(No-1 downto 0);
signal iReset : std_logic;
signal iPLL_Clock : std_logic;

begin
    
	iIn1 <= in1;
	iIn2 <= in2;
	iIn3 <= in3;
	iIn4 <= in4;
	iIn5 <= in5;

	iPLL_Clock <= PLL_Clock;
	iReset <= reset;

	--Some example assignments for reference:
	--iB(0) <= Bin0 XOR Add_or_Sub;
	--Overflow <= not(iBreg(3)) and iSum(3);
	
	Mux1: component MuxN_1 port map
		(
			Input   => iIn1,
			Sel     => iCtrl,
			Output  => iLEDs(0)
		);

	Mux2: component MuxN_1 port map
		(
			Input   => iIn2,
			Sel     => iCtrl,
			Output  => iLEDs(1)
		);

	Mux3: component MuxN_1 port map
		(
			Input   => iIn3,
			Sel     => iCtrl,
			Output  => iLEDs(2)
		);

	Mux4: component MuxN_1 port map
		(
			Input   => iIn4,
			Sel     => iCtrl,
			Output  => iLEDs(3)
		);

	Mux5: component MuxN_1 port map
		(
			Input   => iIn5,
			Sel     => iCtrl,
			Output  => iLEDs(4)
		);

	Counter: component OutputCounter 
		generic map (N =>Ni, S=> S,	E => E)
		port map
		(
			PLL_Clock => iPLL_Clock,
			reset	  => iReset,
			MuxSel    => iCtrl
		);

	LEDs <= iLEDs;
	
	--iCtrl1 = iCtrl2 = iCtrl3 = iCtrl4 = iCtrl5 = iCtrl;

	--Sum3 <= iSum(3);
	--Sum2 <= iSum(2);
	--Sum1 <= iSum(1);
	--Sum0 <= iSum(0);


end structural;