------------------------------------------------- 
-- Increment/Decrement circuit for PLL
-- a divide by 2 on the clock
-- when an inc is recieved the 2 count is upped by 1,
-- this moves the clock ahead a half cycle
-- when a dec is recieved, the clock is lagged a half cycle


library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 

entity MY_ID is 
	port( clock : in std_logic; 
		  increment, decrement : in std_logic;
		  slow_clock : out std_logic  
		); 
end MY_ID; 

architecture behaviour of my_id is 

signal count : std_logic;

begin 

counter :process(clock) 

    begin 
        if rising_edge(clock) then
			if increment = '1' then
			-- increment counter, that is, add two
				if count = '0' then
					-- add two
					-- carry will be produced
               		count <= '0';
					slow_clock <= '1';
				elsif count = '1' then
					count <= '1';
					slow_clock <= '0';
				end if;
			elsif decrement = '1' then
			-- decrement counter. actually just don't increment it
				if count = '0' then 
					count <= '0';
					slow_clock <= '0';
				elsif count = '1' then
					count <= '1';
					slow_clock <= '0';
				end if;
			else
			-- no adjustment requested, count as usual
				if count = '1' then
					count <= '0';
					slow_clock <= '1';
				elsif count = '0' then
					count <= '1';
					slow_clock <= '0';
				end if;
			end if;	
        end if; 
    end process counter; 



end behaviour;