------------------------------------------------- 
-- synchronous counter 
-- 
library ieee; 
use ieee.std_logic_1164.all; 
-- these packages allow math on std_logic
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 

entity MY_DIVN is 
	generic ( width : positive := 8;
			  top_value : positive := 128);
    port( clock : in std_logic; 
		  cout : out std_logic;
		  reset : in std_logic
		  ); 
	-- don't need a q port in this case
	-- carry out is the new clock
	end MY_DIVN; 

architecture behaviour of my_divn is 

signal q : std_logic_vector (width-1 downto 0);

begin 

counter :process(clock,reset) 
--active low reset
    begin 
    if reset = '0' then
   		q <= (others => '0');
   		cout <= '1';
    elsif rising_edge(clock) then 
			if q = top_value then
			-- carry will be produced
               	q <= (others => '0');
				cout <= '1';
			else
				q <= q + 1;
				cout <= '0';
			end if;
       end if; 
   end process counter; 

end behaviour;