------------------------------------------------- 
-- synchronous counter 
-- 
library ieee; 
use ieee.std_logic_1164.all; 
-- these packages allow math on std_logic
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 
entity MY_COUNTER is 
	generic ( width : positive := 8;
			  top_value : positive := 128);
    port( updown, clock : in std_logic; 
		  bout, cout : out std_logic
		  ); 
	-- don't need a q port in this case
	-- using it as part of the inc/dec circuit in the pll
end MY_COUNTER; 

architecture behaviour of my_counter is 

signal q : std_logic_vector (width-1 downto 0);

begin 
counter :process(clock) 

    begin 
        if rising_edge(clock) then 
            if updown = '1' then
			-- counting up 
			-- how to check if counter is at the top? and all the bits together
			-- is there an operator that does this?
				if q = top_value then
				-- carry will be produced
                	q <= (others => '0');
					cout <= '1';
					bout <= '0';
				else
					q <= q + 1;
					cout <= '0';
					bout <= '0';
				end if;
            elsif updown = '0' then
			-- counting down	
				if q = 0 then
				-- borrow will be produced
					q <= (others => '1');
					bout <= '1';
					cout <= '0';
				else
					q <= q - 1;
					bout <= '0';
					cout <= '0';
				end if;
			end if; 
        end if; 
    end process counter; 

end behaviour;