------------------------------------------ -- TOP LEVEL -- this entity contains the PLL and the top component -- with the code for the spinning display library ieee; use ieee.std_logic_1164.all; entity demo_toplevel is generic (numleds : positive := 5); port ( ref_clock : in std_logic; motor_clock : in std_logic; --checksensor : out std_logic; --derived : out std_logic; hrbutton, minbutton : in std_logic; LEDsT, LEDsB : out std_logic_vector (numleds-1 downto 0) ); end demo_toplevel; architecture blocks of demo_toplevel is signal sync_clock, motor_reset : std_logic; signal hflopped, mflopped, reset_one : std_logic; signal int, int2, buttons : std_logic_vector(1 downto 0); ------------------------------------------------------- -- component declarations COMPONENT lpm_ff GENERIC (LPM_WIDTH: POSITIVE; LPM_AVALUE: STRING := "UNUSED"; LPM_PVALUE: STRING := "UNUSED"; LPM_FFTYPE: STRING := "DFF"; LPM_TYPE: STRING := "LPM_FF"; LPM_SVALUE: STRING := "UNUSED"; LPM_HINT: STRING := "UNUSED"); PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0); clock: IN STD_LOGIC; enable: IN STD_LOGIC := '1'; sload: IN STD_LOGIC := '0'; sclr: IN STD_LOGIC := '0'; sset: IN STD_LOGIC := '0'; aload: IN STD_LOGIC := '0'; aclr: IN STD_LOGIC := '0'; aset: IN STD_LOGIC := '0'; q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)); END COMPONENT; --------------------------------------------------------------- component phase_lock_loop is port ( ref : in std_logic; motor : in std_logic; new_clock : buffer std_logic; reset : in std_logic ); end component phase_lock_loop; ------------------------------------------------- component spinning_display is generic (numleds : positive := 5); port ( slow_clock : in std_logic; fast_clock : in std_logic; displayT,displayB : out std_logic_vector (numleds-1 downto 0); minbutton, hrbutton, motor_reset : in std_logic ); end component spinning_display; ------------------------------------------------------ begin buttons <= hrbutton & minbutton; motor_reset <= not motor_clock; --checksensor <= motor_reset; stage_1: COMPONENT lpm_ff GENERIC MAP(LPM_WIDTH=> 2) PORT MAP(data=>buttons, clock => motor_clock, q => int); stage_2: COMPONENT lpm_ff GENERIC MAP(LPM_WIDTH=> 2) PORT MAP(data=>int, clock => motor_clock, q => int2); mflopped<= not int2(0); hflopped <= not int2(1); reset_one <= '1'; clock_mult : component phase_lock_loop port map ( ref=> ref_clock, motor => motor_clock, new_clock => sync_clock, reset => reset_one); main : component spinning_display generic map (numleds => numleds ) port map (fast_clock => ref_clock, slow_clock => sync_clock, displayT => LEDsT, displayB => LEDsB, hrbutton => hflopped, minbutton => mflopped, motor_reset => reset_one); end blocks;