-----------------------
-- EE 552
-- PROJECT MODULE:
-- DESCRIPTION: toplevelmodule for time
-- This entity/architecture takes outputs from the time module and
-- uses a MUX (and counter) to go through each output.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

----------------------------------------------------------------------

entity complete_time is

	port( clock: in std_logic;
		  to_lookup: out std_logic_vector(3 downto 0);
			digit_count : out std_logic_vector(2 downto 0);
			hrbutton, minbutton : in std_logic);
		 
end entity complete_time;
---------------------------------------------------------


architecture toplevel_description of complete_time is
----------------------------------------------------------
--component declarations 

component timeMUX is
    generic( N: positive := 4;	
			 C: positive:= 3);
    port( min_units, min_tens, hour_units, hour_tens 
		     : in std_logic_vector( N-1 downto 0 );
          fromcounter: in std_logic_vector( C-1 downto 0 );
		  MUXout: out std_logic_vector(N-1 downto 0)
	);
end component;
-------------------
component toplevel_timemodule is

	port( clock: in std_logic;
		  hour_tens,hour_units,min_tens,min_units: 
						out std_logic_vector(3 downto 0);
		  seconds_clock: out std_logic;
		  hrbutton, minbutton: in std_logic);


end component;
----------------------
component MUXcounter is
		generic (datawidth :positive :=3 );
        port (clock: in std_logic;
			  thecount: out std_logic_vector(datawidth-1 downto 0) );

end component;
---------------------
component my_divn
	generic ( width : positive := 8;
			  top_value : positive := 128);

    port( clock : in std_logic; 
		  cout : out std_logic;
		  reset : in std_logic); 
end component my_divn;


---------------------------------------------------
---------------------------------------------------
-- INTERNAL SIGNAL -------------------------------

signal hr_tens,hr_units,min_tens,min_units: std_logic_vector(3 downto 0);
signal from_counter : std_logic_vector(2 downto 0);
signal for_MUXcounter : std_logic;
signal dummy, reset_one: std_logic;

begin
reset_one <= '1';

--Map between toplevel_timemodule and internal signals
c0: component toplevel_timemodule   port map(
	clock => clock,
    hour_tens  => hr_tens,
  	hour_units => hr_units,
	min_tens => min_tens,
	min_units => min_units,
	seconds_clock => dummy,
	hrbutton => hrbutton, minbutton => minbutton); 

--Map between MUXcounter and output of toplevel_timmodule
c1: component MUXcounter  port map(
	clock => for_MUXcounter, 
	thecount => from_counter );  
	
c3: component my_divN generic map (width => 22, top_value => 2500000) 
				port map (clock => clock,  cout => for_MUXcounter, reset => reset_one);
	 

--Map between internal signals and timeMUX
c2: component timeMUX port map(
	min_units => min_units,
	min_tens => min_tens,
	hour_units => hr_units,
    hour_tens => hr_tens,
    fromcounter => from_counter,
	MUXout => to_lookup);

digit_count <= from_counter;

end architecture toplevel_description;