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-- N bit Counter
-- Author       : B. Ryan Northcott
-- Student ID   : 252494
-- Date         : Mar 6, 2001
-- File Name    : OutputCounter.vhd
-- Architecture : Behavioral
-- Description  : 
--
-- Acknowledgements:
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library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity OutputCounter is
    generic
	(
		N : positive := 80;	-- Max Count
		S : positive := 10;	-- Start the Top Display
		E : positive := 30;	-- End the Top Display
		C : positive := 5;  -- Number of Mux Control Lines
		D : positive := 7   -- Number of bits in counter
	);
    port
	(
		PLL_Clock : in std_logic;
		reset	  :	in std_logic;
		MuxSel    : out std_logic_vector( C-1 downto 0 )
	);
end OutputCounter;

-- Behavioral Implementation of the counter
architecture behavioral of OutputCounter is
begin
	counter : process(reset, PLL_Clock)
	variable count : std_logic_vector(D-1 downto 0);
    begin
		if reset = '0' then -- active low reset
			count := (others => '0');
			MuxSel <= "10101";  -- 21 in binary
        elsif rising_edge(PLL_Clock) then
			if count = 79 then	-- this line gives width mismatch in relational operator 
								--(only in newer version of maxplus2)
								-- compiles fine when i use 79 instead of N-1?????	
				count := (others => '0');
			else
            	count := count + 1;
			end if;
			if (count >= 9) and (count <= 29) then
            	MuxSel <= count - (S-1); 
			else
				MuxSel <= "10101";  -- 21 in binary
			end if;
        end if;
	end process counter;
end behavioral;